2N/A/*
2N/A * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
2N/A * Use is subject to license terms.
2N/A */
2N/A
2N/A/*
2N/A * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved.
2N/A *
2N/A * Redistribution and use in source and binary forms, with or without
2N/A * modification, are permitted provided that the following conditions are met:
2N/A *
2N/A * + Redistributions of source code must retain the above copyright notice,
2N/A * + this list of conditions and the following disclaimer.
2N/A *
2N/A * + Redistributions in binary form must reproduce the above copyright
2N/A * + notice, this list of conditions and the following disclaimer in the
2N/A * + documentation and/or other materials provided with the distribution.
2N/A *
2N/A * + Neither the name of Advanced Micro Devices, Inc. nor the names of its
2N/A * + contributors may be used to endorse or promote products derived from
2N/A * + this software without specific prior written permission.
2N/A *
2N/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
2N/A * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
2N/A * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2N/A * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
2N/A * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR
2N/A * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2N/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2N/A * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2N/A * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2N/A * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2N/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
2N/A * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
2N/A * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2N/A *
2N/A * Import/Export/Re-Export/Use/Release/Transfer Restrictions and
2N/A * Compliance with Applicable Laws. Notice is hereby given that
2N/A * the software may be subject to restrictions on use, release,
2N/A * transfer, importation, exportation and/or re-exportation under
2N/A * the laws and regulations of the United States or other
2N/A * countries ("Applicable Laws"), which include but are not
2N/A * limited to U.S. export control laws such as the Export
2N/A * Administration Regulations and national security controls as
2N/A * defined thereunder, as well as State Department controls under
2N/A * the U.S. Munitions List. Permission to use and/or
2N/A * redistribute the software is conditioned upon compliance with
2N/A * all Applicable Laws, including U.S. export control laws
2N/A * regarding specifically designated persons, countries and
2N/A * nationals of countries subject to national security controls.
2N/A */
2N/A
2N/A/* include files */
2N/A#include <sys/disp.h>
2N/A#include <sys/atomic.h>
2N/A#include <sys/vlan.h>
2N/A#include "amd8111s_main.h"
2N/A
2N/A/* Global macro Definations */
2N/A#define ROUNDUP(x, a) (((x) + (a) - 1) & ~((a) - 1))
2N/A#define INTERFACE_NAME "amd8111s"
2N/A#define AMD8111S_SPLIT 128
2N/A#define AMD8111S_SEND_MAX 64
2N/A
2N/Astatic char ident[] = "AMD8111 10/100M Ethernet";
2N/A
2N/A/*
2N/A * Driver Entry Points
2N/A */
2N/Astatic int amd8111s_attach(dev_info_t *, ddi_attach_cmd_t);
2N/Astatic int amd8111s_detach(dev_info_t *, ddi_detach_cmd_t);
2N/A
2N/A/*
2N/A * GLD Entry points prototype
2N/A */
2N/Astatic int amd8111s_m_unicst(void *, const uint8_t *);
2N/Astatic int amd8111s_m_promisc(void *, boolean_t);
2N/Astatic int amd8111s_m_stat(void *, uint_t, uint64_t *);
2N/Astatic void amd8111s_m_ioctl(void *, queue_t *, mblk_t *);
2N/Astatic int amd8111s_m_multicst(void *, boolean_t, const uint8_t *addr);
2N/Astatic int amd8111s_m_start(void *);
2N/Astatic void amd8111s_m_stop(void *);
2N/Astatic mblk_t *amd8111s_m_tx(void *, mblk_t *mp);
2N/Astatic uint_t amd8111s_intr(caddr_t);
2N/A
2N/Astatic int amd8111s_unattach(dev_info_t *, struct LayerPointers *);
2N/A
2N/Astatic boolean_t amd8111s_allocate_buffers(struct LayerPointers *);
2N/Astatic int amd8111s_odlInit(struct LayerPointers *);
2N/Astatic boolean_t amd8111s_allocate_descriptors(struct LayerPointers *);
2N/Astatic void amd8111s_free_descriptors(struct LayerPointers *);
2N/Astatic boolean_t amd8111s_alloc_dma_ringbuf(struct LayerPointers *,
2N/A struct amd8111s_dma_ringbuf *, uint32_t, uint32_t);
2N/Astatic void amd8111s_free_dma_ringbuf(struct amd8111s_dma_ringbuf *);
2N/A
2N/A
2N/Astatic void amd8111s_log(struct LayerPointers *adapter, int level,
2N/A char *fmt, ...);
2N/A
2N/Astatic struct cb_ops amd8111s_cb_ops = {
2N/A nulldev,
2N/A nulldev,
2N/A nodev,
2N/A nodev,
2N/A nodev,
2N/A nodev,
2N/A nodev,
2N/A nodev,
2N/A nodev,
2N/A nodev,
2N/A nodev,
2N/A nochpoll,
2N/A ddi_prop_op,
2N/A NULL,
2N/A D_NEW | D_MP,
2N/A CB_REV, /* cb_rev */
2N/A nodev, /* cb_aread */
2N/A nodev /* cb_awrite */
2N/A};
2N/A
2N/Astatic struct dev_ops amd8111s_dev_ops = {
2N/A DEVO_REV, /* devo_rev */
2N/A 0, /* devo_refcnt */
2N/A NULL, /* devo_getinfo */
2N/A nulldev, /* devo_identify */
2N/A nulldev, /* devo_probe */
2N/A amd8111s_attach, /* devo_attach */
2N/A amd8111s_detach, /* devo_detach */
2N/A nodev, /* devo_reset */
2N/A &amd8111s_cb_ops, /* devo_cb_ops */
2N/A NULL, /* devo_bus_ops */
2N/A nodev, /* devo_power */
2N/A ddi_quiesce_not_supported, /* devo_quiesce */
2N/A};
2N/A
2N/Astruct modldrv amd8111s_modldrv = {
2N/A &mod_driverops, /* Type of module. This one is a driver */
2N/A ident, /* short description */
2N/A &amd8111s_dev_ops /* driver specific ops */
2N/A};
2N/A
2N/Astruct modlinkage amd8111s_modlinkage = {
2N/A MODREV_1, (void *)&amd8111s_modldrv, NULL
2N/A};
2N/A
2N/A/*
2N/A * Global Variables
2N/A */
2N/Astruct LayerPointers *amd8111sadapter;
2N/A
2N/Astatic ddi_dma_attr_t pcn_buff_dma_attr_t = {
2N/A DMA_ATTR_V0, /* dma_attr_version */
2N/A (uint64_t)0, /* dma_attr_addr_lo */
2N/A (uint64_t)0xFFFFFFFF, /* dma_attr_addr_hi */
2N/A (uint64_t)0xFFFFFFFF, /* dma_attr_count_max */
2N/A (uint64_t)1, /* dma_attr_align */
2N/A (uint_t)0x7F, /* dma_attr_burstsizes */
2N/A (uint32_t)1, /* dma_attr_minxfer */
2N/A (uint64_t)0xFFFFFFFF, /* dma_attr_maxxfer */
2N/A (uint64_t)0xFFFFFFFF, /* dma_attr_seg */
2N/A (int)1, /* dma_attr_sgllen */
2N/A (uint32_t)1, /* granularity */
2N/A (uint_t)0 /* dma_attr_flags */
2N/A};
2N/A
2N/Astatic ddi_dma_attr_t pcn_desc_dma_attr_t = {
2N/A DMA_ATTR_V0, /* dma_attr_version */
2N/A (uint64_t)0, /* dma_attr_addr_lo */
2N/A (uint64_t)0xFFFFFFFF, /* dma_attr_addr_hi */
2N/A (uint64_t)0x7FFFFFFF, /* dma_attr_count_max */
2N/A (uint64_t)0x10, /* dma_attr_align */
2N/A (uint_t)0xFFFFFFFFU, /* dma_attr_burstsizes */
2N/A (uint32_t)1, /* dma_attr_minxfer */
2N/A (uint64_t)0xFFFFFFFF, /* dma_attr_maxxfer */
2N/A (uint64_t)0xFFFFFFFF, /* dma_attr_seg */
2N/A (int)1, /* dma_attr_sgllen */
2N/A (uint32_t)1, /* granularity */
2N/A (uint_t)0 /* dma_attr_flags */
2N/A};
2N/A
2N/A/* PIO access attributes for registers */
2N/Astatic ddi_device_acc_attr_t pcn_acc_attr = {
2N/A DDI_DEVICE_ATTR_V0,
2N/A DDI_STRUCTURE_LE_ACC,
2N/A DDI_STRICTORDER_ACC
2N/A};
2N/A
2N/A
2N/Astatic mac_callbacks_t amd8111s_m_callbacks = {
2N/A MC_IOCTL,
2N/A amd8111s_m_stat,
2N/A amd8111s_m_start,
2N/A amd8111s_m_stop,
2N/A amd8111s_m_promisc,
2N/A amd8111s_m_multicst,
2N/A amd8111s_m_unicst,
2N/A amd8111s_m_tx,
2N/A NULL,
2N/A amd8111s_m_ioctl
2N/A};
2N/A
2N/A
2N/A/*
2N/A * Standard Driver Load Entry Point
2N/A * It will be called at load time of driver.
2N/A */
2N/Aint
2N/A_init()
2N/A{
2N/A int status;
2N/A mac_init_ops(&amd8111s_dev_ops, "amd8111s");
2N/A
2N/A status = mod_install(&amd8111s_modlinkage);
2N/A if (status != DDI_SUCCESS) {
2N/A mac_fini_ops(&amd8111s_dev_ops);
2N/A }
2N/A
2N/A return (status);
2N/A}
2N/A
2N/A/*
2N/A * Standard Driver Entry Point for Query.
2N/A * It will be called at any time to get Driver info.
2N/A */
2N/Aint
2N/A_info(struct modinfo *modinfop)
2N/A{
2N/A return (mod_info(&amd8111s_modlinkage, modinfop));
2N/A}
2N/A
2N/A/*
2N/A * Standard Driver Entry Point for Unload.
2N/A * It will be called at unload time of driver.
2N/A */
2N/Aint
2N/A_fini()
2N/A{
2N/A int status;
2N/A
2N/A status = mod_remove(&amd8111s_modlinkage);
2N/A if (status == DDI_SUCCESS) {
2N/A mac_fini_ops(&amd8111s_dev_ops);
2N/A }
2N/A
2N/A return (status);
2N/A}
2N/A
2N/A/*
2N/A * Loopback Support
2N/A */
2N/Astatic lb_property_t loopmodes[] = {
2N/A { normal, "normal", AMD8111S_LB_NONE },
2N/A { external, "100Mbps", AMD8111S_LB_EXTERNAL_100 },
2N/A { external, "10Mbps", AMD8111S_LB_EXTERNAL_10 },
2N/A { internal, "MAC", AMD8111S_LB_INTERNAL_MAC }
2N/A};
2N/A
2N/Astatic void
2N/Aamd8111s_set_loop_mode(struct LayerPointers *adapter, uint32_t mode)
2N/A{
2N/A
2N/A /*
2N/A * If the mode isn't being changed, there's nothing to do ...
2N/A */
2N/A if (mode == adapter->pOdl->loopback_mode)
2N/A return;
2N/A
2N/A /*
2N/A * Validate the requested mode and prepare a suitable message
2N/A * to explain the link down/up cycle that the change will
2N/A * probably induce ...
2N/A */
2N/A switch (mode) {
2N/A default:
2N/A return;
2N/A
2N/A case AMD8111S_LB_NONE:
2N/A mdlStopChip(adapter);
2N/A if (adapter->pOdl->loopback_mode == AMD8111S_LB_INTERNAL_MAC) {
2N/A cmn_err(CE_NOTE, "LB_NONE restored from Interanl LB");
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
2N/A INLOOP);
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD3,
2N/A FORCE_FULL_DUPLEX | FORCE_LINK_STATUS);
2N/A } else {
2N/A cmn_err(CE_NOTE, "LB_NONE restored from Exteranl LB");
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
2N/A EXLOOP);
2N/A }
2N/A
2N/A amd8111s_reset(adapter);
2N/A adapter->pOdl->LinkStatus = LINK_STATE_DOWN;
2N/A adapter->pOdl->rx_fcs_stripped = B_FALSE;
2N/A mdlStartChip(adapter);
2N/A break;
2N/A
2N/A case AMD8111S_LB_EXTERNAL_100:
2N/A cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_EXTERNAL_100");
2N/A mdlStopChip(adapter);
2N/A amd8111s_reset(adapter);
2N/A SetIntrCoalesc(adapter, B_FALSE);
2N/A mdlPHYAutoNegotiation(adapter, PHY_FORCE_FD_100);
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
2N/A VAL0 | EXLOOP);
2N/A adapter->pOdl->LinkStatus = LINK_STATE_UP;
2N/A adapter->pMdl->Speed = 100;
2N/A adapter->pMdl->FullDuplex = B_TRUE;
2N/A /* Tell GLD the state of the physical link. */
2N/A mac_link_update(adapter->pOdl->mh, LINK_STATE_UP);
2N/A
2N/A adapter->pOdl->rx_fcs_stripped = B_TRUE;
2N/A
2N/A mdlStartChip(adapter);
2N/A break;
2N/A
2N/A case AMD8111S_LB_EXTERNAL_10:
2N/A cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_EXTERNAL_10");
2N/A mdlStopChip(adapter);
2N/A amd8111s_reset(adapter);
2N/A SetIntrCoalesc(adapter, B_FALSE);
2N/A mdlPHYAutoNegotiation(adapter, PHY_FORCE_FD_10);
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
2N/A VAL0 | EXLOOP);
2N/A adapter->pOdl->LinkStatus = LINK_STATE_UP;
2N/A adapter->pMdl->Speed = 10;
2N/A adapter->pMdl->FullDuplex = B_TRUE;
2N/A /* Tell GLD the state of the physical link. */
2N/A mac_link_update(adapter->pOdl->mh, LINK_STATE_UP);
2N/A
2N/A adapter->pOdl->rx_fcs_stripped = B_TRUE;
2N/A
2N/A mdlStartChip(adapter);
2N/A break;
2N/A
2N/A case AMD8111S_LB_INTERNAL_MAC:
2N/A cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_INTERNAL_MAC");
2N/A mdlStopChip(adapter);
2N/A amd8111s_reset(adapter);
2N/A SetIntrCoalesc(adapter, B_FALSE);
2N/A /* Disable Port Manager */
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD3,
2N/A EN_PMGR);
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
2N/A VAL0 | INLOOP);
2N/A
2N/A WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD3,
2N/A VAL1 | FORCE_FULL_DUPLEX | FORCE_LINK_STATUS);
2N/A
2N/A adapter->pOdl->LinkStatus = LINK_STATE_UP;
2N/A adapter->pMdl->FullDuplex = B_TRUE;
2N/A /* Tell GLD the state of the physical link. */
2N/A mac_link_update(adapter->pOdl->mh, LINK_STATE_UP);
2N/A
2N/A adapter->pOdl->rx_fcs_stripped = B_TRUE;
2N/A
2N/A mdlStartChip(adapter);
2N/A break;
2N/A }
2N/A
2N/A /*
2N/A * All OK; tell the caller to reprogram
2N/A * the PHY and/or MAC for the new mode ...
2N/A */
2N/A adapter->pOdl->loopback_mode = mode;
2N/A}
2N/A
2N/Astatic enum ioc_reply
2N/Aamd8111s_loopback_ioctl(struct LayerPointers *adapter, struct iocblk *iocp,
2N/A mblk_t *mp)
2N/A{
2N/A lb_info_sz_t *lbsp;
2N/A lb_property_t *lbpp;
2N/A uint32_t *lbmp;
2N/A int cmd;
2N/A
2N/A /*
2N/A * Validate format of ioctl
2N/A */
2N/A if (mp->b_cont == NULL)
2N/A return (IOC_INVAL);
2N/A
2N/A cmd = iocp->ioc_cmd;
2N/A switch (cmd) {
2N/A default:
2N/A /* NOTREACHED */
2N/A amd8111s_log(adapter, CE_NOTE,
2N/A "amd8111s_loop_ioctl: invalid cmd 0x%x", cmd);
2N/A return (IOC_INVAL);
2N/A
2N/A case LB_GET_INFO_SIZE:
2N/A if (iocp->ioc_count != sizeof (lb_info_sz_t)) {
2N/A amd8111s_log(adapter, CE_NOTE,
2N/A "wrong LB_GET_INFO_SIZE size");
2N/A return (IOC_INVAL);
2N/A }
2N/A lbsp = (void *)mp->b_cont->b_rptr;
2N/A *lbsp = sizeof (loopmodes);
2N/A break;
2N/A
2N/A case LB_GET_INFO:
2N/A if (iocp->ioc_count != sizeof (loopmodes)) {
2N/A amd8111s_log(adapter, CE_NOTE,
2N/A "Wrong LB_GET_INFO size");
2N/A return (IOC_INVAL);
2N/A }
2N/A lbpp = (void *)mp->b_cont->b_rptr;
2N/A bcopy(loopmodes, lbpp, sizeof (loopmodes));
2N/A break;
2N/A
2N/A case LB_GET_MODE:
2N/A if (iocp->ioc_count != sizeof (uint32_t)) {
2N/A amd8111s_log(adapter, CE_NOTE,
2N/A "Wrong LB_GET_MODE size");
2N/A return (IOC_INVAL);
2N/A }
2N/A lbmp = (void *)mp->b_cont->b_rptr;
2N/A *lbmp = adapter->pOdl->loopback_mode;
2N/A break;
2N/A
2N/A case LB_SET_MODE:
2N/A if (iocp->ioc_count != sizeof (uint32_t)) {
2N/A amd8111s_log(adapter, CE_NOTE,
2N/A "Wrong LB_SET_MODE size");
2N/A return (IOC_INVAL);
2N/A }
2N/A lbmp = (void *)mp->b_cont->b_rptr;
2N/A amd8111s_set_loop_mode(adapter, *lbmp);
2N/A break;
2N/A }
2N/A return (IOC_REPLY);
2N/A}
2N/A
2N/Astatic void
2N/Aamd8111s_m_ioctl(void *arg, queue_t *q, mblk_t *mp)
2N/A{
2N/A struct iocblk *iocp;
2N/A struct LayerPointers *adapter;
2N/A enum ioc_reply status;
2N/A
2N/A iocp = (void *)mp->b_rptr;
2N/A iocp->ioc_error = 0;
2N/A adapter = arg;
2N/A
2N/A ASSERT(adapter);
2N/A if (adapter == NULL) {
2N/A miocnak(q, mp, 0, EINVAL);
2N/A return;
2N/A }
2N/A
2N/A switch (iocp->ioc_cmd) {
2N/A
2N/A case LB_GET_INFO_SIZE:
2N/A case LB_GET_INFO:
2N/A case LB_GET_MODE:
2N/A case LB_SET_MODE:
2N/A status = amd8111s_loopback_ioctl(adapter, iocp, mp);
2N/A break;
2N/A
2N/A default:
2N/A status = IOC_INVAL;
2N/A break;
2N/A }
2N/A
2N/A /*
2N/A * Decide how to reply
2N/A */
2N/A switch (status) {
2N/A default:
2N/A case IOC_INVAL:
2N/A /*
2N/A * Error, reply with a NAK and EINVAL or the specified error
2N/A */
2N/A miocnak(q, mp, 0, iocp->ioc_error == 0 ?
2N/A EINVAL : iocp->ioc_error);
2N/A break;
2N/A
2N/A case IOC_DONE:
2N/A /*
2N/A * OK, reply already sent
2N/A */
2N/A break;
2N/A
2N/A case IOC_ACK:
2N/A /*
2N/A * OK, reply with an ACK
2N/A */
2N/A miocack(q, mp, 0, 0);
2N/A break;
2N/A
2N/A case IOC_REPLY:
2N/A /*
2N/A * OK, send prepared reply as ACK or NAK
2N/A */
2N/A mp->b_datap->db_type = iocp->ioc_error == 0 ?
2N/A M_IOCACK : M_IOCNAK;
2N/A qreply(q, mp);
2N/A break;
2N/A }
2N/A}
2N/A
2N/A/*
2N/A * Copy one packet from dma memory to mblk. Inc dma descriptor pointer.
2N/A */
2N/Astatic boolean_t
2N/Aamd8111s_recv_copy(struct LayerPointers *pLayerPointers, mblk_t **last_mp)
2N/A{
2N/A int length = 0;
2N/A mblk_t *mp;
2N/A struct rx_desc *descriptor;
2N/A struct odl *pOdl = pLayerPointers->pOdl;
2N/A struct amd8111s_statistics *statistics = &pOdl->statistics;
2N/A struct nonphysical *pNonphysical = pLayerPointers->pMil
2N/A ->pNonphysical;
2N/A
2N/A mutex_enter(&pOdl->mdlRcvLock);
2N/A descriptor = pNonphysical->RxBufDescQRead->descriptor;
2N/A (void) ddi_dma_sync(pOdl->rx_desc_dma_handle,
2N/A pNonphysical->RxBufDescQRead->descriptor -
2N/A pNonphysical->RxBufDescQStart->descriptor,
2N/A sizeof (struct rx_desc), DDI_DMA_SYNC_FORCPU);
2N/A if ((descriptor->Rx_OWN) == 0) {
2N/A /*
2N/A * If the frame is received with errors, then set MCNT
2N/A * of that pkt in ReceiveArray to 0. This packet would
2N/A * be discarded later and not indicated to OS.
2N/A */
2N/A if (descriptor->Rx_ERR) {
2N/A statistics->rx_desc_err ++;
2N/A descriptor->Rx_ERR = 0;
2N/A if (descriptor->Rx_FRAM == 1) {
2N/A statistics->rx_desc_err_FRAM ++;
2N/A descriptor->Rx_FRAM = 0;
2N/A }
2N/A if (descriptor->Rx_OFLO == 1) {
2N/A statistics->rx_desc_err_OFLO ++;
2N/A descriptor->Rx_OFLO = 0;
2N/A pOdl->rx_overflow_counter ++;
2N/A if ((pOdl->rx_overflow_counter > 5) &&
2N/A (pOdl->pause_interval == 0)) {
2N/A statistics->rx_double_overflow ++;
2N/A mdlSendPause(pLayerPointers);
2N/A pOdl->rx_overflow_counter = 0;
2N/A pOdl->pause_interval = 25;
2N/A }
2N/A }
2N/A if (descriptor->Rx_CRC == 1) {
2N/A statistics->rx_desc_err_CRC ++;
2N/A descriptor->Rx_CRC = 0;
2N/A }
2N/A if (descriptor->Rx_BUFF == 1) {
2N/A statistics->rx_desc_err_BUFF ++;
2N/A descriptor->Rx_BUFF = 0;
2N/A }
2N/A goto Next_Descriptor;
2N/A }
2N/A
2N/A /* Length of incoming packet */
2N/A if (pOdl->rx_fcs_stripped) {
2N/A length = descriptor->Rx_MCNT -4;
2N/A } else {
2N/A length = descriptor->Rx_MCNT;
2N/A }
2N/A if (length < 62) {
2N/A statistics->rx_error_zerosize ++;
2N/A }
2N/A
2N/A if ((mp = allocb(length, BPRI_MED)) == NULL) {
2N/A statistics->rx_allocfail ++;
2N/A goto failed;
2N/A }
2N/A /* Copy from virtual address of incoming packet */
2N/A bcopy((long *)*(pNonphysical->RxBufDescQRead->USpaceMap),
2N/A mp->b_rptr, length);
2N/A mp->b_wptr = mp->b_rptr + length;
2N/A statistics->rx_ok_packets ++;
2N/A if (*last_mp == NULL) {
2N/A *last_mp = mp;
2N/A } else {
2N/A (*last_mp)->b_next = mp;
2N/A *last_mp = mp;
2N/A }
2N/A
2N/ANext_Descriptor:
2N/A descriptor->Rx_MCNT = 0;
2N/A descriptor->Rx_SOP = 0;
2N/A descriptor->Rx_EOP = 0;
2N/A descriptor->Rx_PAM = 0;
2N/A descriptor->Rx_BAM = 0;
2N/A descriptor->TT = 0;
2N/A descriptor->Rx_OWN = 1;
2N/A pNonphysical->RxBufDescQRead->descriptor++;
2N/A pNonphysical->RxBufDescQRead->USpaceMap++;
2N/A if (pNonphysical->RxBufDescQRead->descriptor >
2N/A pNonphysical->RxBufDescQEnd->descriptor) {
2N/A pNonphysical->RxBufDescQRead->descriptor =
2N/A pNonphysical->RxBufDescQStart->descriptor;
2N/A pNonphysical->RxBufDescQRead->USpaceMap =
2N/A pNonphysical->RxBufDescQStart->USpaceMap;
2N/A }
2N/A mutex_exit(&pOdl->mdlRcvLock);
2N/A
2N/A return (B_TRUE);
2N/A }
2N/A
2N/Afailed:
2N/A mutex_exit(&pOdl->mdlRcvLock);
2N/A return (B_FALSE);
2N/A}
2N/A
2N/A/*
2N/A * Get the received packets from NIC card and send them to GLD.
2N/A */
2N/Astatic void
2N/Aamd8111s_receive(struct LayerPointers *pLayerPointers)
2N/A{
2N/A int numOfPkts = 0;
2N/A struct odl *pOdl;
2N/A mblk_t *ret_mp = NULL, *last_mp = NULL;
2N/A
2N/A pOdl = pLayerPointers->pOdl;
2N/A
2N/A rw_enter(&pOdl->chip_lock, RW_READER);
2N/A if (!pLayerPointers->run) {
2N/A rw_exit(&pOdl->chip_lock);
2N/A return;
2N/A }
2N/A
2N/A if (pOdl->pause_interval > 0)
2N/A pOdl->pause_interval --;
2N/A
2N/A while (numOfPkts < RX_RING_SIZE) {
2N/A
2N/A if (!amd8111s_recv_copy(pLayerPointers, &last_mp)) {
2N/A break;
2N/A }
2N/A if (ret_mp == NULL)
2N/A ret_mp = last_mp;
2N/A numOfPkts++;
2N/A }
2N/A
2N/A if (ret_mp) {
2N/A mac_rx(pOdl->mh, NULL, ret_mp);
2N/A }
2N/A
2N/A (void) ddi_dma_sync(pOdl->rx_desc_dma_handle, 0, 0,
2N/A DDI_DMA_SYNC_FORDEV);
2N/A
2N/A mdlReceive(pLayerPointers);
2N/A
2N/A rw_exit(&pOdl->chip_lock);
2N/A
2N/A}
2N/A
2N/A/*
2N/A * Print message in release-version driver.
2N/A */
2N/Astatic void
2N/Aamd8111s_log(struct LayerPointers *adapter, int level, char *fmt, ...)
2N/A{
2N/A auto char name[32];
2N/A auto char buf[256];
2N/A va_list ap;
2N/A
2N/A if (adapter != NULL) {
2N/A (void) sprintf(name, "amd8111s%d",
2N/A ddi_get_instance(adapter->pOdl->devinfo));
2N/A } else {
2N/A (void) sprintf(name, "amd8111s");
2N/A }
2N/A va_start(ap, fmt);
2N/A (void) vsprintf(buf, fmt, ap);
2N/A va_end(ap);
2N/A cmn_err(level, "%s: %s", name, buf);
2N/A}
2N/A
2N/A/*
2N/A * To allocate & initilize all resources.
2N/A * Called by amd8111s_attach().
2N/A */
2N/Astatic int
2N/Aamd8111s_odlInit(struct LayerPointers *pLayerPointers)
2N/A{
2N/A unsigned long mem_req_array[MEM_REQ_MAX];
2N/A unsigned long mem_set_array[MEM_REQ_MAX];
2N/A unsigned long *pmem_req_array;
2N/A unsigned long *pmem_set_array;
2N/A int i, size;
2N/A
2N/A for (i = 0; i < MEM_REQ_MAX; i++) {
2N/A mem_req_array[i] = 0;
2N/A mem_set_array[i] = 0;
2N/A }
2N/A
2N/A milRequestResources(mem_req_array);
2N/A
2N/A pmem_req_array = mem_req_array;
2N/A pmem_set_array = mem_set_array;
2N/A while (*pmem_req_array) {
2N/A switch (*pmem_req_array) {
2N/A case VIRTUAL:
2N/A *pmem_set_array = VIRTUAL;
2N/A pmem_req_array++;
2N/A pmem_set_array++;
2N/A *(pmem_set_array) = *(pmem_req_array);
2N/A pmem_set_array++;
2N/A *(pmem_set_array) = (unsigned long) kmem_zalloc(
2N/A *(pmem_req_array), KM_NOSLEEP);
2N/A if (*pmem_set_array == NULL)
2N/A goto odl_init_failure;
2N/A break;
2N/A }
2N/A pmem_req_array++;
2N/A pmem_set_array++;
2N/A }
2N/A
2N/A /*
2N/A * Initilize memory on lower layers
2N/A */
2N/A milSetResources(pLayerPointers, mem_set_array);
2N/A
2N/A /* Allocate Rx/Tx descriptors */
2N/A if (amd8111s_allocate_descriptors(pLayerPointers) != B_TRUE) {
2N/A *pmem_set_array = NULL;
2N/A goto odl_init_failure;
2N/A }
2N/A
2N/A /*
2N/A * Allocate Rx buffer for each Rx descriptor. Then call mil layer
2N/A * routine to fill physical address of Rx buffer into Rx descriptor.
2N/A */
2N/A if (amd8111s_allocate_buffers(pLayerPointers) == B_FALSE) {
2N/A amd8111s_free_descriptors(pLayerPointers);
2N/A *pmem_set_array = NULL;
2N/A goto odl_init_failure;
2N/A }
2N/A milInitGlbds(pLayerPointers);
2N/A
2N/A return (0);
2N/A
2N/Aodl_init_failure:
2N/A /*
2N/A * Free All memory allocated so far
2N/A */
2N/A pmem_req_array = mem_set_array;
2N/A while ((*pmem_req_array) && (pmem_req_array != pmem_set_array)) {
2N/A switch (*pmem_req_array) {
2N/A case VIRTUAL:
2N/A pmem_req_array++; /* Size */
2N/A size = *(pmem_req_array);
2N/A pmem_req_array++; /* Virtual Address */
2N/A if (pmem_req_array == NULL)
2N/A return (1);
2N/A kmem_free((int *)*pmem_req_array, size);
2N/A break;
2N/A }
2N/A pmem_req_array++;
2N/A }
2N/A return (1);
2N/A}
2N/A
2N/A/*
2N/A * Allocate and initialize Tx/Rx descriptors
2N/A */
2N/Astatic boolean_t
2N/Aamd8111s_allocate_descriptors(struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct odl *pOdl = pLayerPointers->pOdl;
2N/A struct mil *pMil = pLayerPointers->pMil;
2N/A dev_info_t *devinfo = pOdl->devinfo;
2N/A uint_t length, count, i;
2N/A size_t real_length;
2N/A
2N/A /*
2N/A * Allocate Rx descriptors
2N/A */
2N/A if (ddi_dma_alloc_handle(devinfo, &pcn_desc_dma_attr_t, DDI_DMA_SLEEP,
2N/A NULL, &pOdl->rx_desc_dma_handle) != DDI_SUCCESS) {
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_alloc_handle for Rx desc failed");
2N/A pOdl->rx_desc_dma_handle = NULL;
2N/A return (B_FALSE);
2N/A }
2N/A
2N/A length = sizeof (struct rx_desc) * RX_RING_SIZE + ALIGNMENT;
2N/A if (ddi_dma_mem_alloc(pOdl->rx_desc_dma_handle, length,
2N/A &pcn_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
2N/A NULL, (caddr_t *)&pMil->Rx_desc_original, &real_length,
2N/A &pOdl->rx_desc_acc_handle) != DDI_SUCCESS) {
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_mem_handle for Rx desc failed");
2N/A ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
2N/A pOdl->rx_desc_dma_handle = NULL;
2N/A return (B_FALSE);
2N/A }
2N/A
2N/A if (ddi_dma_addr_bind_handle(pOdl->rx_desc_dma_handle,
2N/A NULL, (caddr_t)pMil->Rx_desc_original, real_length,
2N/A DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
2N/A NULL, &pOdl->rx_desc_dma_cookie,
2N/A &count) != DDI_SUCCESS) {
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_addr_bind_handle for Rx desc failed");
2N/A ddi_dma_mem_free(&pOdl->rx_desc_acc_handle);
2N/A ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
2N/A pOdl->rx_desc_dma_handle = NULL;
2N/A return (B_FALSE);
2N/A }
2N/A ASSERT(count == 1);
2N/A
2N/A /* Initialize Rx descriptors related variables */
2N/A pMil->Rx_desc = (struct rx_desc *)
2N/A ((pMil->Rx_desc_original + ALIGNMENT) & ~ALIGNMENT);
2N/A pMil->Rx_desc_pa = (unsigned int)
2N/A ((pOdl->rx_desc_dma_cookie.dmac_laddress + ALIGNMENT) & ~ALIGNMENT);
2N/A
2N/A pLayerPointers->pMdl->init_blk->RDRA = pMil->Rx_desc_pa;
2N/A
2N/A
2N/A /*
2N/A * Allocate Tx descriptors
2N/A */
2N/A if (ddi_dma_alloc_handle(devinfo, &pcn_desc_dma_attr_t, DDI_DMA_SLEEP,
2N/A NULL, &pOdl->tx_desc_dma_handle) != DDI_SUCCESS) {
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_alloc_handle for Tx desc failed");
2N/A goto allocate_desc_fail;
2N/A }
2N/A
2N/A length = sizeof (struct tx_desc) * TX_RING_SIZE + ALIGNMENT;
2N/A if (ddi_dma_mem_alloc(pOdl->tx_desc_dma_handle, length,
2N/A &pcn_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
2N/A NULL, (caddr_t *)&pMil->Tx_desc_original, &real_length,
2N/A &pOdl->tx_desc_acc_handle) != DDI_SUCCESS) {
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_mem_handle for Tx desc failed");
2N/A ddi_dma_free_handle(&pOdl->tx_desc_dma_handle);
2N/A goto allocate_desc_fail;
2N/A }
2N/A
2N/A if (ddi_dma_addr_bind_handle(pOdl->tx_desc_dma_handle,
2N/A NULL, (caddr_t)pMil->Tx_desc_original, real_length,
2N/A DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
2N/A NULL, &pOdl->tx_desc_dma_cookie,
2N/A &count) != DDI_SUCCESS) {
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_addr_bind_handle for Tx desc failed");
2N/A ddi_dma_mem_free(&pOdl->tx_desc_acc_handle);
2N/A ddi_dma_free_handle(&pOdl->tx_desc_dma_handle);
2N/A goto allocate_desc_fail;
2N/A }
2N/A ASSERT(count == 1);
2N/A /* Set the DMA area to all zeros */
2N/A bzero((caddr_t)pMil->Tx_desc_original, length);
2N/A
2N/A /* Initialize Tx descriptors related variables */
2N/A pMil->Tx_desc = (struct tx_desc *)
2N/A ((pMil->Tx_desc_original + ALIGNMENT) & ~ALIGNMENT);
2N/A pMil->pNonphysical->TxDescQRead = pMil->Tx_desc;
2N/A pMil->pNonphysical->TxDescQWrite = pMil->Tx_desc;
2N/A pMil->pNonphysical->TxDescQStart = pMil->Tx_desc;
2N/A pMil->pNonphysical->TxDescQEnd = &(pMil->Tx_desc[TX_RING_SIZE -1]);
2N/A
2N/A /* Physical Addr of Tx_desc_original & Tx_desc */
2N/A pLayerPointers->pMil->Tx_desc_pa =
2N/A ((pOdl->tx_desc_dma_cookie.dmac_laddress + ALIGNMENT) &
2N/A ~ALIGNMENT);
2N/A
2N/A /* Setting the reserved bits in the tx descriptors */
2N/A for (i = 0; i < TX_RING_SIZE; i++) {
2N/A pMil->pNonphysical->TxDescQWrite->Tx_RES0 = 0x0f;
2N/A pMil->pNonphysical->TxDescQWrite->Tx_OWN = 0;
2N/A pMil->pNonphysical->TxDescQWrite++;
2N/A }
2N/A pMil->pNonphysical->TxDescQWrite = pMil->pNonphysical->TxDescQStart;
2N/A
2N/A pLayerPointers->pMdl->init_blk->TDRA = pMil->Tx_desc_pa;
2N/A
2N/A return (B_TRUE);
2N/A
2N/Aallocate_desc_fail:
2N/A pOdl->tx_desc_dma_handle = NULL;
2N/A (void) ddi_dma_unbind_handle(pOdl->rx_desc_dma_handle);
2N/A ddi_dma_mem_free(&pOdl->rx_desc_acc_handle);
2N/A ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
2N/A pOdl->rx_desc_dma_handle = NULL;
2N/A return (B_FALSE);
2N/A}
2N/A
2N/A/*
2N/A * Free Tx/Rx descriptors
2N/A */
2N/Astatic void
2N/Aamd8111s_free_descriptors(struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct odl *pOdl = pLayerPointers->pOdl;
2N/A
2N/A /* Free Rx descriptors */
2N/A if (pOdl->rx_desc_dma_handle) {
2N/A (void) ddi_dma_unbind_handle(pOdl->rx_desc_dma_handle);
2N/A ddi_dma_mem_free(&pOdl->rx_desc_acc_handle);
2N/A ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
2N/A pOdl->rx_desc_dma_handle = NULL;
2N/A }
2N/A
2N/A /* Free Rx descriptors */
2N/A if (pOdl->tx_desc_dma_handle) {
2N/A (void) ddi_dma_unbind_handle(pOdl->tx_desc_dma_handle);
2N/A ddi_dma_mem_free(&pOdl->tx_desc_acc_handle);
2N/A ddi_dma_free_handle(&pOdl->tx_desc_dma_handle);
2N/A pOdl->tx_desc_dma_handle = NULL;
2N/A }
2N/A}
2N/A
2N/A/*
2N/A * Allocate Tx/Rx Ring buffer
2N/A */
2N/Astatic boolean_t
2N/Aamd8111s_alloc_dma_ringbuf(struct LayerPointers *pLayerPointers,
2N/A struct amd8111s_dma_ringbuf *pRing,
2N/A uint32_t ring_size, uint32_t msg_size)
2N/A{
2N/A uint32_t idx, msg_idx = 0, msg_acc;
2N/A dev_info_t *devinfo = pLayerPointers->pOdl->devinfo;
2N/A size_t real_length;
2N/A uint_t count = 0;
2N/A
2N/A ASSERT(pcn_buff_dma_attr_t.dma_attr_align == 1);
2N/A pRing->dma_buf_sz = msg_size;
2N/A pRing->ring_size = ring_size;
2N/A pRing->trunk_num = AMD8111S_SPLIT;
2N/A pRing->buf_sz = msg_size * ring_size;
2N/A if (ring_size < pRing->trunk_num)
2N/A pRing->trunk_num = ring_size;
2N/A ASSERT((pRing->buf_sz % pRing->trunk_num) == 0);
2N/A
2N/A pRing->trunk_sz = pRing->buf_sz / pRing->trunk_num;
2N/A ASSERT((pRing->trunk_sz % pRing->dma_buf_sz) == 0);
2N/A
2N/A pRing->msg_buf = kmem_zalloc(sizeof (struct amd8111s_msgbuf) *
2N/A ring_size, KM_NOSLEEP);
2N/A pRing->dma_hdl = kmem_zalloc(sizeof (ddi_dma_handle_t) *
2N/A pRing->trunk_num, KM_NOSLEEP);
2N/A pRing->acc_hdl = kmem_zalloc(sizeof (ddi_acc_handle_t) *
2N/A pRing->trunk_num, KM_NOSLEEP);
2N/A pRing->dma_cookie = kmem_zalloc(sizeof (ddi_dma_cookie_t) *
2N/A pRing->trunk_num, KM_NOSLEEP);
2N/A pRing->trunk_addr = kmem_zalloc(sizeof (caddr_t) *
2N/A pRing->trunk_num, KM_NOSLEEP);
2N/A if (pRing->msg_buf == NULL || pRing->dma_hdl == NULL ||
2N/A pRing->acc_hdl == NULL || pRing->trunk_addr == NULL ||
2N/A pRing->dma_cookie == NULL) {
2N/A amd8111s_log(pLayerPointers, CE_NOTE,
2N/A "kmem_zalloc failed");
2N/A goto failed;
2N/A }
2N/A
2N/A for (idx = 0; idx < pRing->trunk_num; ++idx) {
2N/A if (ddi_dma_alloc_handle(devinfo, &pcn_buff_dma_attr_t,
2N/A DDI_DMA_SLEEP, NULL, &(pRing->dma_hdl[idx]))
2N/A != DDI_SUCCESS) {
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_alloc_handle failed");
2N/A goto failed;
2N/A } else if (ddi_dma_mem_alloc(pRing->dma_hdl[idx],
2N/A pRing->trunk_sz, &pcn_acc_attr, DDI_DMA_STREAMING,
2N/A DDI_DMA_SLEEP, NULL,
2N/A (caddr_t *)&(pRing->trunk_addr[idx]),
2N/A (size_t *)(&real_length), &pRing->acc_hdl[idx])
2N/A != DDI_SUCCESS) {
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_mem_alloc failed");
2N/A goto failed;
2N/A } else if (real_length != pRing->trunk_sz) {
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_mem_alloc failed");
2N/A goto failed;
2N/A } else if (ddi_dma_addr_bind_handle(pRing->dma_hdl[idx],
2N/A NULL, (caddr_t)pRing->trunk_addr[idx], real_length,
2N/A DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL,
2N/A &pRing->dma_cookie[idx], &count) != DDI_DMA_MAPPED) {
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "ddi_dma_addr_bind_handle failed");
2N/A goto failed;
2N/A } else {
2N/A for (msg_acc = 0;
2N/A msg_acc < pRing->trunk_sz / pRing->dma_buf_sz;
2N/A ++ msg_acc) {
2N/A pRing->msg_buf[msg_idx].offset =
2N/A msg_acc * pRing->dma_buf_sz;
2N/A pRing->msg_buf[msg_idx].vir_addr =
2N/A pRing->trunk_addr[idx] +
2N/A pRing->msg_buf[msg_idx].offset;
2N/A pRing->msg_buf[msg_idx].phy_addr =
2N/A pRing->dma_cookie[idx].dmac_laddress +
2N/A pRing->msg_buf[msg_idx].offset;
2N/A pRing->msg_buf[msg_idx].p_hdl =
2N/A pRing->dma_hdl[idx];
2N/A msg_idx ++;
2N/A }
2N/A }
2N/A }
2N/A
2N/A pRing->free = pRing->msg_buf;
2N/A pRing->next = pRing->msg_buf;
2N/A pRing->curr = pRing->msg_buf;
2N/A
2N/A return (B_TRUE);
2N/Afailed:
2N/A amd8111s_free_dma_ringbuf(pRing);
2N/A return (B_FALSE);
2N/A}
2N/A
2N/A/*
2N/A * Free Tx/Rx ring buffer
2N/A */
2N/Astatic void
2N/Aamd8111s_free_dma_ringbuf(struct amd8111s_dma_ringbuf *pRing)
2N/A{
2N/A int idx;
2N/A
2N/A if (pRing->dma_cookie != NULL) {
2N/A for (idx = 0; idx < pRing->trunk_num; idx ++) {
2N/A if (pRing->dma_cookie[idx].dmac_laddress == 0) {
2N/A break;
2N/A }
2N/A (void) ddi_dma_unbind_handle(pRing->dma_hdl[idx]);
2N/A }
2N/A kmem_free(pRing->dma_cookie,
2N/A sizeof (ddi_dma_cookie_t) * pRing->trunk_num);
2N/A }
2N/A
2N/A if (pRing->acc_hdl != NULL) {
2N/A for (idx = 0; idx < pRing->trunk_num; idx ++) {
2N/A if (pRing->acc_hdl[idx] == NULL)
2N/A break;
2N/A ddi_dma_mem_free(&pRing->acc_hdl[idx]);
2N/A }
2N/A kmem_free(pRing->acc_hdl,
2N/A sizeof (ddi_acc_handle_t) * pRing->trunk_num);
2N/A }
2N/A
2N/A if (pRing->dma_hdl != NULL) {
2N/A for (idx = 0; idx < pRing->trunk_num; idx ++) {
2N/A if (pRing->dma_hdl[idx] == 0) {
2N/A break;
2N/A }
2N/A ddi_dma_free_handle(&pRing->dma_hdl[idx]);
2N/A }
2N/A kmem_free(pRing->dma_hdl,
2N/A sizeof (ddi_dma_handle_t) * pRing->trunk_num);
2N/A }
2N/A
2N/A if (pRing->msg_buf != NULL) {
2N/A kmem_free(pRing->msg_buf,
2N/A sizeof (struct amd8111s_msgbuf) * pRing->ring_size);
2N/A }
2N/A
2N/A if (pRing->trunk_addr != NULL) {
2N/A kmem_free(pRing->trunk_addr,
2N/A sizeof (caddr_t) * pRing->trunk_num);
2N/A }
2N/A
2N/A bzero(pRing, sizeof (*pRing));
2N/A}
2N/A
2N/A
2N/A/*
2N/A * Allocate all Tx buffer.
2N/A * Allocate a Rx buffer for each Rx descriptor. Then
2N/A * call mil routine to fill physical address of Rx
2N/A * buffer into Rx descriptors
2N/A */
2N/Astatic boolean_t
2N/Aamd8111s_allocate_buffers(struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct odl *pOdl = pLayerPointers->pOdl;
2N/A
2N/A /*
2N/A * Allocate rx Buffers
2N/A */
2N/A if (amd8111s_alloc_dma_ringbuf(pLayerPointers, &pOdl->rx_buf,
2N/A RX_RING_SIZE, RX_BUF_SIZE) == B_FALSE) {
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "amd8111s_alloc_dma_ringbuf for tx failed");
2N/A goto allocate_buf_fail;
2N/A }
2N/A
2N/A /*
2N/A * Allocate Tx buffers
2N/A */
2N/A if (amd8111s_alloc_dma_ringbuf(pLayerPointers, &pOdl->tx_buf,
2N/A TX_COALESC_SIZE, TX_BUF_SIZE) == B_FALSE) {
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "amd8111s_alloc_dma_ringbuf for tx failed");
2N/A goto allocate_buf_fail;
2N/A }
2N/A
2N/A /*
2N/A * Initilize the mil Queues
2N/A */
2N/A milInitGlbds(pLayerPointers);
2N/A
2N/A milInitRxQ(pLayerPointers);
2N/A
2N/A return (B_TRUE);
2N/A
2N/Aallocate_buf_fail:
2N/A
2N/A amd8111s_log(pLayerPointers, CE_WARN,
2N/A "amd8111s_allocate_buffers failed");
2N/A return (B_FALSE);
2N/A}
2N/A
2N/A/*
2N/A * Free all Rx/Tx buffer
2N/A */
2N/A
2N/Astatic void
2N/Aamd8111s_free_buffers(struct LayerPointers *pLayerPointers)
2N/A{
2N/A /* Free Tx buffers */
2N/A amd8111s_free_dma_ringbuf(&pLayerPointers->pOdl->tx_buf);
2N/A
2N/A /* Free Rx Buffers */
2N/A amd8111s_free_dma_ringbuf(&pLayerPointers->pOdl->rx_buf);
2N/A}
2N/A
2N/A/*
2N/A * Try to recycle all the descriptors and Tx buffers
2N/A * which are already freed by hardware.
2N/A */
2N/Astatic int
2N/Aamd8111s_recycle_tx(struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct nonphysical *pNonphysical;
2N/A uint32_t count = 0;
2N/A
2N/A pNonphysical = pLayerPointers->pMil->pNonphysical;
2N/A while (pNonphysical->TxDescQRead->Tx_OWN == 0 &&
2N/A pNonphysical->TxDescQRead != pNonphysical->TxDescQWrite) {
2N/A pLayerPointers->pOdl->tx_buf.free =
2N/A NEXT(pLayerPointers->pOdl->tx_buf, free);
2N/A pNonphysical->TxDescQRead++;
2N/A if (pNonphysical->TxDescQRead > pNonphysical->TxDescQEnd) {
2N/A pNonphysical->TxDescQRead = pNonphysical->TxDescQStart;
2N/A }
2N/A count ++;
2N/A }
2N/A
2N/A if (pLayerPointers->pMil->tx_reschedule)
2N/A ddi_trigger_softintr(pLayerPointers->pOdl->drain_id);
2N/A
2N/A return (count);
2N/A}
2N/A
2N/A/*
2N/A * Get packets in the Tx buffer, then copy them to the send buffer.
2N/A * Trigger hardware to send out packets.
2N/A */
2N/Astatic void
2N/Aamd8111s_send_serial(struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct nonphysical *pNonphysical;
2N/A uint32_t count;
2N/A
2N/A pNonphysical = pLayerPointers->pMil->pNonphysical;
2N/A
2N/A mutex_enter(&pLayerPointers->pOdl->mdlSendLock);
2N/A
2N/A for (count = 0; count < AMD8111S_SEND_MAX; count ++) {
2N/A if (pLayerPointers->pOdl->tx_buf.curr ==
2N/A pLayerPointers->pOdl->tx_buf.next) {
2N/A break;
2N/A }
2N/A /* to verify if it needs to recycle the tx Buf */
2N/A if (((pNonphysical->TxDescQWrite + 1 >
2N/A pNonphysical->TxDescQEnd) ? pNonphysical->TxDescQStart :
2N/A (pNonphysical->TxDescQWrite + 1)) ==
2N/A pNonphysical->TxDescQRead)
2N/A if (amd8111s_recycle_tx(pLayerPointers) == 0) {
2N/A pLayerPointers->pOdl
2N/A ->statistics.tx_no_descriptor ++;
2N/A break;
2N/A }
2N/A
2N/A /* Fill packet length */
2N/A pNonphysical->TxDescQWrite->Tx_BCNT = (uint16_t)pLayerPointers
2N/A ->pOdl->tx_buf.curr->msg_size;
2N/A
2N/A /* Fill physical buffer address */
2N/A pNonphysical->TxDescQWrite->Tx_Base_Addr = (unsigned int)
2N/A pLayerPointers->pOdl->tx_buf.curr->phy_addr;
2N/A
2N/A pNonphysical->TxDescQWrite->Tx_SOP = 1;
2N/A pNonphysical->TxDescQWrite->Tx_EOP = 1;
2N/A pNonphysical->TxDescQWrite->Tx_ADD_FCS = 1;
2N/A pNonphysical->TxDescQWrite->Tx_LTINT = 1;
2N/A pNonphysical->TxDescQWrite->Tx_USPACE = 0;
2N/A pNonphysical->TxDescQWrite->Tx_OWN = 1;
2N/A
2N/A pNonphysical->TxDescQWrite++;
2N/A if (pNonphysical->TxDescQWrite > pNonphysical->TxDescQEnd) {
2N/A pNonphysical->TxDescQWrite = pNonphysical->TxDescQStart;
2N/A }
2N/A
2N/A pLayerPointers->pOdl->tx_buf.curr =
2N/A NEXT(pLayerPointers->pOdl->tx_buf, curr);
2N/A
2N/A }
2N/A
2N/A pLayerPointers->pOdl->statistics.tx_ok_packets += count;
2N/A
2N/A mutex_exit(&pLayerPointers->pOdl->mdlSendLock);
2N/A
2N/A /* Call mdlTransmit to send the pkt out on the network */
2N/A mdlTransmit(pLayerPointers);
2N/A
2N/A}
2N/A
2N/A/*
2N/A * Softintr entrance. try to send out packets in the Tx buffer.
2N/A * If reschedule is True, call mac_tx_update to re-enable the
2N/A * transmit
2N/A */
2N/Astatic uint_t
2N/Aamd8111s_send_drain(caddr_t arg)
2N/A{
2N/A struct LayerPointers *pLayerPointers = (void *)arg;
2N/A
2N/A amd8111s_send_serial(pLayerPointers);
2N/A
2N/A if (pLayerPointers->pMil->tx_reschedule &&
2N/A NEXT(pLayerPointers->pOdl->tx_buf, next) !=
2N/A pLayerPointers->pOdl->tx_buf.free) {
2N/A mac_tx_update(pLayerPointers->pOdl->mh);
2N/A pLayerPointers->pMil->tx_reschedule = B_FALSE;
2N/A }
2N/A
2N/A return (DDI_INTR_CLAIMED);
2N/A}
2N/A
2N/A/*
2N/A * Get a Tx buffer
2N/A */
2N/Astatic struct amd8111s_msgbuf *
2N/Aamd8111s_getTxbuf(struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct amd8111s_msgbuf *tmp, *next;
2N/A
2N/A mutex_enter(&pLayerPointers->pOdl->mdlSendLock);
2N/A next = NEXT(pLayerPointers->pOdl->tx_buf, next);
2N/A if (next == pLayerPointers->pOdl->tx_buf.free) {
2N/A tmp = NULL;
2N/A } else {
2N/A tmp = pLayerPointers->pOdl->tx_buf.next;
2N/A pLayerPointers->pOdl->tx_buf.next = next;
2N/A }
2N/A mutex_exit(&pLayerPointers->pOdl->mdlSendLock);
2N/A
2N/A return (tmp);
2N/A}
2N/A
2N/Astatic boolean_t
2N/Aamd8111s_send(struct LayerPointers *pLayerPointers, mblk_t *mp)
2N/A{
2N/A struct odl *pOdl;
2N/A size_t frag_len;
2N/A mblk_t *tmp;
2N/A struct amd8111s_msgbuf *txBuf;
2N/A uint8_t *pMsg;
2N/A
2N/A pOdl = pLayerPointers->pOdl;
2N/A
2N/A /* alloc send buffer */
2N/A txBuf = amd8111s_getTxbuf(pLayerPointers);
2N/A if (txBuf == NULL) {
2N/A pOdl->statistics.tx_no_buffer ++;
2N/A pLayerPointers->pMil->tx_reschedule = B_TRUE;
2N/A amd8111s_send_serial(pLayerPointers);
2N/A return (B_FALSE);
2N/A }
2N/A
2N/A /* copy packet to send buffer */
2N/A txBuf->msg_size = 0;
2N/A pMsg = (uint8_t *)txBuf->vir_addr;
2N/A for (tmp = mp; tmp; tmp = tmp->b_cont) {
2N/A frag_len = MBLKL(tmp);
2N/A bcopy(tmp->b_rptr, pMsg, frag_len);
2N/A txBuf->msg_size += frag_len;
2N/A pMsg += frag_len;
2N/A }
2N/A freemsg(mp);
2N/A
2N/A amd8111s_send_serial(pLayerPointers);
2N/A
2N/A return (B_TRUE);
2N/A}
2N/A
2N/A/*
2N/A * (GLD Entry Point) Send the message block to lower layer
2N/A */
2N/Astatic mblk_t *
2N/Aamd8111s_m_tx(void *arg, mblk_t *mp)
2N/A{
2N/A struct LayerPointers *pLayerPointers = arg;
2N/A mblk_t *next;
2N/A
2N/A rw_enter(&pLayerPointers->pOdl->chip_lock, RW_READER);
2N/A if (!pLayerPointers->run) {
2N/A pLayerPointers->pOdl->statistics.tx_afterunplumb ++;
2N/A freemsgchain(mp);
2N/A mp = NULL;
2N/A }
2N/A
2N/A while (mp != NULL) {
2N/A next = mp->b_next;
2N/A mp->b_next = NULL;
2N/A if (!amd8111s_send(pLayerPointers, mp)) {
2N/A /* Send fail */
2N/A mp->b_next = next;
2N/A break;
2N/A }
2N/A mp = next;
2N/A }
2N/A
2N/A rw_exit(&pLayerPointers->pOdl->chip_lock);
2N/A return (mp);
2N/A}
2N/A
2N/A/*
2N/A * (GLD Entry Point) Interrupt Service Routine
2N/A */
2N/Astatic uint_t
2N/Aamd8111s_intr(caddr_t arg)
2N/A{
2N/A unsigned int intrCauses;
2N/A struct LayerPointers *pLayerPointers = (void *)arg;
2N/A
2N/A /* Read the interrupt status from mdl */
2N/A intrCauses = mdlReadInterrupt(pLayerPointers);
2N/A
2N/A if (intrCauses == 0) {
2N/A pLayerPointers->pOdl->statistics.intr_OTHER ++;
2N/A return (DDI_INTR_UNCLAIMED);
2N/A }
2N/A
2N/A if (intrCauses & LCINT) {
2N/A if (mdlReadLink(pLayerPointers) == LINK_UP) {
2N/A mdlGetActiveMediaInfo(pLayerPointers);
2N/A /* Link status changed */
2N/A if (pLayerPointers->pOdl->LinkStatus !=
2N/A LINK_STATE_UP) {
2N/A pLayerPointers->pOdl->LinkStatus =
2N/A LINK_STATE_UP;
2N/A mac_link_update(pLayerPointers->pOdl->mh,
2N/A LINK_STATE_UP);
2N/A }
2N/A } else {
2N/A if (pLayerPointers->pOdl->LinkStatus !=
2N/A LINK_STATE_DOWN) {
2N/A pLayerPointers->pOdl->LinkStatus =
2N/A LINK_STATE_DOWN;
2N/A mac_link_update(pLayerPointers->pOdl->mh,
2N/A LINK_STATE_DOWN);
2N/A }
2N/A }
2N/A }
2N/A /*
2N/A * RINT0: Receive Interrupt is set by the controller after the last
2N/A * descriptor of a receive frame for this ring has been updated by
2N/A * writing a 0 to the OWNership bit.
2N/A */
2N/A if (intrCauses & RINT0) {
2N/A pLayerPointers->pOdl->statistics.intr_RINT0 ++;
2N/A amd8111s_receive(pLayerPointers);
2N/A }
2N/A
2N/A /*
2N/A * TINT0: Transmit Interrupt is set by the controller after the OWN bit
2N/A * in the last descriptor of a transmit frame in this particular ring
2N/A * has been cleared to indicate the frame has been copied to the
2N/A * transmit FIFO.
2N/A */
2N/A if (intrCauses & TINT0) {
2N/A pLayerPointers->pOdl->statistics.intr_TINT0 ++;
2N/A /*
2N/A * if desc ring is NULL and tx buf is not NULL, it should
2N/A * drain tx buffer
2N/A */
2N/A amd8111s_send_serial(pLayerPointers);
2N/A }
2N/A
2N/A if (intrCauses & STINT) {
2N/A pLayerPointers->pOdl->statistics.intr_STINT ++;
2N/A }
2N/A
2N/A
2N/A return (DDI_INTR_CLAIMED);
2N/A}
2N/A
2N/A/*
2N/A * To re-initilize data structures.
2N/A */
2N/Astatic void
2N/Aamd8111s_sw_reset(struct LayerPointers *pLayerPointers)
2N/A{
2N/A /* Reset all Tx/Rx queues and descriptors */
2N/A milResetTxQ(pLayerPointers);
2N/A milInitRxQ(pLayerPointers);
2N/A}
2N/A
2N/A/*
2N/A * Send all pending tx packets
2N/A */
2N/Astatic void
2N/Aamd8111s_tx_drain(struct LayerPointers *adapter)
2N/A{
2N/A struct tx_desc *pTx_desc = adapter->pMil->pNonphysical->TxDescQStart;
2N/A int i, desc_count = 0;
2N/A for (i = 0; i < 30; i++) {
2N/A while ((pTx_desc->Tx_OWN == 0) && (desc_count < TX_RING_SIZE)) {
2N/A /* This packet has been transmitted */
2N/A pTx_desc ++;
2N/A desc_count ++;
2N/A }
2N/A if (desc_count == TX_RING_SIZE) {
2N/A break;
2N/A }
2N/A /* Wait 1 ms */
2N/A drv_usecwait(1000);
2N/A }
2N/A adapter->pOdl->statistics.tx_draintime = i;
2N/A}
2N/A
2N/A/*
2N/A * (GLD Entry Point) To start card will be called at
2N/A * ifconfig plumb
2N/A */
2N/Astatic int
2N/Aamd8111s_m_start(void *arg)
2N/A{
2N/A struct LayerPointers *pLayerPointers = arg;
2N/A struct odl *pOdl = pLayerPointers->pOdl;
2N/A
2N/A amd8111s_sw_reset(pLayerPointers);
2N/A mdlHWReset(pLayerPointers);
2N/A rw_enter(&pOdl->chip_lock, RW_WRITER);
2N/A pLayerPointers->run = B_TRUE;
2N/A rw_exit(&pOdl->chip_lock);
2N/A return (0);
2N/A}
2N/A
2N/A/*
2N/A * (GLD Entry Point) To stop card will be called at
2N/A * ifconfig unplumb
2N/A */
2N/Astatic void
2N/Aamd8111s_m_stop(void *arg)
2N/A{
2N/A struct LayerPointers *pLayerPointers = (struct LayerPointers *)arg;
2N/A struct odl *pOdl = pLayerPointers->pOdl;
2N/A
2N/A /* Ensure send all pending tx packets */
2N/A amd8111s_tx_drain(pLayerPointers);
2N/A /*
2N/A * Stop the controller and disable the controller interrupt
2N/A */
2N/A rw_enter(&pOdl->chip_lock, RW_WRITER);
2N/A mdlStopChip(pLayerPointers);
2N/A pLayerPointers->run = B_FALSE;
2N/A rw_exit(&pOdl->chip_lock);
2N/A}
2N/A
2N/A/*
2N/A * To clean up all
2N/A */
2N/Astatic void
2N/Aamd8111s_free_resource(struct LayerPointers *pLayerPointers)
2N/A{
2N/A unsigned long mem_free_array[100];
2N/A unsigned long *pmem_free_array, size;
2N/A
2N/A /* Free Rx/Tx descriptors */
2N/A amd8111s_free_descriptors(pLayerPointers);
2N/A
2N/A /* Free memory on lower layers */
2N/A milFreeResources(pLayerPointers, mem_free_array);
2N/A pmem_free_array = mem_free_array;
2N/A while (*pmem_free_array) {
2N/A switch (*pmem_free_array) {
2N/A case VIRTUAL:
2N/A size = *(++pmem_free_array);
2N/A pmem_free_array++;
2N/A kmem_free((void *)*(pmem_free_array), size);
2N/A break;
2N/A }
2N/A pmem_free_array++;
2N/A }
2N/A
2N/A amd8111s_free_buffers(pLayerPointers);
2N/A}
2N/A
2N/A/*
2N/A * (GLD Enty pointer) To add/delete multi cast addresses
2N/A *
2N/A */
2N/Astatic int
2N/Aamd8111s_m_multicst(void *arg, boolean_t add, const uint8_t *addr)
2N/A{
2N/A struct LayerPointers *pLayerPointers = arg;
2N/A
2N/A if (add) {
2N/A /* Add a multicast entry */
2N/A mdlAddMulticastAddress(pLayerPointers, (UCHAR *)addr);
2N/A } else {
2N/A /* Delete a multicast entry */
2N/A mdlDeleteMulticastAddress(pLayerPointers, (UCHAR *)addr);
2N/A }
2N/A
2N/A return (0);
2N/A}
2N/A
2N/A#ifdef AMD8111S_DEBUG
2N/A/*
2N/A * The size of MIB registers is only 32 bits. Dump them before one
2N/A * of them overflows.
2N/A */
2N/Astatic void
2N/Aamd8111s_dump_mib(struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct amd8111s_statistics *adapterStat;
2N/A
2N/A adapterStat = &pLayerPointers->pOdl->statistics;
2N/A
2N/A adapterStat->mib_dump_counter ++;
2N/A
2N/A /*
2N/A * Rx Counters
2N/A */
2N/A adapterStat->rx_mib_unicst_packets +=
2N/A mdlReadMib(pLayerPointers, RcvUniCastPkts);
2N/A adapterStat->rx_mib_multicst_packets +=
2N/A mdlReadMib(pLayerPointers, RcvMultiCastPkts);
2N/A adapterStat->rx_mib_broadcst_packets +=
2N/A mdlReadMib(pLayerPointers, RcvBroadCastPkts);
2N/A adapterStat->rx_mib_macctrl_packets +=
2N/A mdlReadMib(pLayerPointers, RcvMACCtrl);
2N/A adapterStat->rx_mib_flowctrl_packets +=
2N/A mdlReadMib(pLayerPointers, RcvFlowCtrl);
2N/A
2N/A adapterStat->rx_mib_bytes +=
2N/A mdlReadMib(pLayerPointers, RcvOctets);
2N/A adapterStat->rx_mib_good_bytes +=
2N/A mdlReadMib(pLayerPointers, RcvGoodOctets);
2N/A
2N/A adapterStat->rx_mib_undersize_packets +=
2N/A mdlReadMib(pLayerPointers, RcvUndersizePkts);
2N/A adapterStat->rx_mib_oversize_packets +=
2N/A mdlReadMib(pLayerPointers, RcvOversizePkts);
2N/A
2N/A adapterStat->rx_mib_drop_packets +=
2N/A mdlReadMib(pLayerPointers, RcvDropPktsRing0);
2N/A adapterStat->rx_mib_align_err_packets +=
2N/A mdlReadMib(pLayerPointers, RcvAlignmentErrors);
2N/A adapterStat->rx_mib_fcs_err_packets +=
2N/A mdlReadMib(pLayerPointers, RcvFCSErrors);
2N/A adapterStat->rx_mib_symbol_err_packets +=
2N/A mdlReadMib(pLayerPointers, RcvSymbolErrors);
2N/A adapterStat->rx_mib_miss_packets +=
2N/A mdlReadMib(pLayerPointers, RcvMissPkts);
2N/A
2N/A /*
2N/A * Tx Counters
2N/A */
2N/A adapterStat->tx_mib_packets +=
2N/A mdlReadMib(pLayerPointers, XmtPackets);
2N/A adapterStat->tx_mib_multicst_packets +=
2N/A mdlReadMib(pLayerPointers, XmtMultiCastPkts);
2N/A adapterStat->tx_mib_broadcst_packets +=
2N/A mdlReadMib(pLayerPointers, XmtBroadCastPkts);
2N/A adapterStat->tx_mib_flowctrl_packets +=
2N/A mdlReadMib(pLayerPointers, XmtFlowCtrl);
2N/A
2N/A adapterStat->tx_mib_bytes +=
2N/A mdlReadMib(pLayerPointers, XmtOctets);
2N/A
2N/A adapterStat->tx_mib_defer_trans_packets +=
2N/A mdlReadMib(pLayerPointers, XmtDeferredTransmit);
2N/A adapterStat->tx_mib_collision_packets +=
2N/A mdlReadMib(pLayerPointers, XmtCollisions);
2N/A adapterStat->tx_mib_one_coll_packets +=
2N/A mdlReadMib(pLayerPointers, XmtOneCollision);
2N/A adapterStat->tx_mib_multi_coll_packets +=
2N/A mdlReadMib(pLayerPointers, XmtMultipleCollision);
2N/A adapterStat->tx_mib_late_coll_packets +=
2N/A mdlReadMib(pLayerPointers, XmtLateCollision);
2N/A adapterStat->tx_mib_ex_coll_packets +=
2N/A mdlReadMib(pLayerPointers, XmtExcessiveCollision);
2N/A
2N/A
2N/A /* Clear all MIB registers */
2N/A WRITE_REG16(pLayerPointers, pLayerPointers->pMdl->Mem_Address
2N/A + MIB_ADDR, MIB_CLEAR);
2N/A}
2N/A#endif
2N/A
2N/A/*
2N/A * (GLD Entry Point) set/unset promiscus mode
2N/A */
2N/Astatic int
2N/Aamd8111s_m_promisc(void *arg, boolean_t on)
2N/A{
2N/A struct LayerPointers *pLayerPointers = arg;
2N/A
2N/A if (on) {
2N/A mdlSetPromiscuous(pLayerPointers);
2N/A } else {
2N/A mdlDisablePromiscuous(pLayerPointers);
2N/A }
2N/A
2N/A return (0);
2N/A}
2N/A
2N/A/*
2N/A * (Gld Entry point) Changes the Mac address of card
2N/A */
2N/Astatic int
2N/Aamd8111s_m_unicst(void *arg, const uint8_t *macaddr)
2N/A{
2N/A struct LayerPointers *pLayerPointers = arg;
2N/A
2N/A mdlDisableInterrupt(pLayerPointers);
2N/A mdlSetMacAddress(pLayerPointers, (unsigned char *)macaddr);
2N/A mdlEnableInterrupt(pLayerPointers);
2N/A
2N/A return (0);
2N/A}
2N/A
2N/A/*
2N/A * Reset the card
2N/A */
2N/Avoid
2N/Aamd8111s_reset(struct LayerPointers *pLayerPointers)
2N/A{
2N/A amd8111s_sw_reset(pLayerPointers);
2N/A mdlHWReset(pLayerPointers);
2N/A}
2N/A
2N/A/*
2N/A * attach(9E) -- Attach a device to the system
2N/A *
2N/A * Called once for each board after successfully probed.
2N/A * will do
2N/A * a. creating minor device node for the instance.
2N/A * b. allocate & Initilize four layers (call odlInit)
2N/A * c. get MAC address
2N/A * d. initilize pLayerPointers to gld private pointer
2N/A * e. register with GLD
2N/A * if any action fails does clean up & returns DDI_FAILURE
2N/A * else retursn DDI_SUCCESS
2N/A */
2N/Astatic int
2N/Aamd8111s_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2N/A{
2N/A mac_register_t *macp;
2N/A struct LayerPointers *pLayerPointers;
2N/A struct odl *pOdl;
2N/A ddi_acc_handle_t *pci_handle;
2N/A ddi_device_acc_attr_t dev_attr;
2N/A caddr_t addrp = NULL;
2N/A
2N/A switch (cmd) {
2N/A case DDI_ATTACH:
2N/A break;
2N/A default:
2N/A return (DDI_FAILURE);
2N/A }
2N/A
2N/A pLayerPointers = (struct LayerPointers *)
2N/A kmem_zalloc(sizeof (struct LayerPointers), KM_SLEEP);
2N/A amd8111sadapter = pLayerPointers;
2N/A
2N/A /* Get device instance number */
2N/A pLayerPointers->instance = ddi_get_instance(devinfo);
2N/A ddi_set_driver_private(devinfo, (caddr_t)pLayerPointers);
2N/A
2N/A pOdl = (struct odl *)kmem_zalloc(sizeof (struct odl), KM_SLEEP);
2N/A pLayerPointers->pOdl = pOdl;
2N/A
2N/A pOdl->devinfo = devinfo;
2N/A
2N/A /*
2N/A * Here, we only allocate memory for struct odl and initilize it.
2N/A * All other memory allocation & initilization will be done in odlInit
2N/A * later on this routine.
2N/A */
2N/A if (ddi_get_iblock_cookie(devinfo, 0, &pLayerPointers->pOdl->iblock)
2N/A != DDI_SUCCESS) {
2N/A amd8111s_log(pLayerPointers, CE_NOTE,
2N/A "attach: get iblock cookies failed");
2N/A goto attach_failure;
2N/A }
2N/A
2N/A rw_init(&pOdl->chip_lock, NULL, RW_DRIVER, (void *)pOdl->iblock);
2N/A mutex_init(&pOdl->mdlSendLock, "amd8111s Send Protection Lock",
2N/A MUTEX_DRIVER, (void *)pOdl->iblock);
2N/A mutex_init(&pOdl->mdlRcvLock, "amd8111s Rcv Protection Lock",
2N/A MUTEX_DRIVER, (void *)pOdl->iblock);
2N/A
2N/A /* Setup PCI space */
2N/A if (pci_config_setup(devinfo, &pOdl->pci_handle) != DDI_SUCCESS) {
2N/A return (DDI_FAILURE);
2N/A }
2N/A pLayerPointers->attach_progress = AMD8111S_ATTACH_PCI;
2N/A pci_handle = &pOdl->pci_handle;
2N/A
2N/A pOdl->vendor_id = pci_config_get16(*pci_handle, PCI_CONF_VENID);
2N/A pOdl->device_id = pci_config_get16(*pci_handle, PCI_CONF_DEVID);
2N/A
2N/A /*
2N/A * Allocate and initialize all resource and map device registers.
2N/A * If failed, it returns a non-zero value.
2N/A */
2N/A if (amd8111s_odlInit(pLayerPointers) != 0) {
2N/A goto attach_failure;
2N/A }
2N/A pLayerPointers->attach_progress |= AMD8111S_ATTACH_RESOURCE;
2N/A
2N/A dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
2N/A dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
2N/A dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
2N/A
2N/A if (ddi_regs_map_setup(devinfo, 1, &addrp, 0, 4096, &dev_attr,
2N/A &(pLayerPointers->pOdl->MemBasehandle)) != 0) {
2N/A amd8111s_log(pLayerPointers, CE_NOTE,
2N/A "attach: ddi_regs_map_setup failed");
2N/A goto attach_failure;
2N/A }
2N/A pLayerPointers->pMdl->Mem_Address = (unsigned long)addrp;
2N/A
2N/A /* Initialize HW */
2N/A mdlOpen(pLayerPointers);
2N/A mdlGetActiveMediaInfo(pLayerPointers);
2N/A pLayerPointers->attach_progress |= AMD8111S_ATTACH_REGS;
2N/A
2N/A /*
2N/A * Setup the interrupt
2N/A */
2N/A if (ddi_add_intr(devinfo, 0, &pOdl->iblock, 0, amd8111s_intr,
2N/A (caddr_t)pLayerPointers) != DDI_SUCCESS) {
2N/A goto attach_failure;
2N/A }
2N/A pLayerPointers->attach_progress |= AMD8111S_ATTACH_INTRADDED;
2N/A
2N/A /*
2N/A * Setup soft intr
2N/A */
2N/A if (ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &pOdl->drain_id,
2N/A NULL, NULL, amd8111s_send_drain,
2N/A (caddr_t)pLayerPointers) != DDI_SUCCESS) {
2N/A goto attach_failure;
2N/A }
2N/A pLayerPointers->attach_progress |= AMD8111S_ATTACH_RESCHED;
2N/A
2N/A /*
2N/A * Initilize the mac structure
2N/A */
2N/A if ((macp = mac_alloc(MAC_VERSION)) == NULL)
2N/A goto attach_failure;
2N/A
2N/A macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
2N/A macp->m_driver = pLayerPointers;
2N/A macp->m_dip = devinfo;
2N/A /* Get MAC address */
2N/A mdlGetMacAddress(pLayerPointers, (unsigned char *)pOdl->MacAddress);
2N/A macp->m_src_addr = pOdl->MacAddress;
2N/A macp->m_callbacks = &amd8111s_m_callbacks;
2N/A macp->m_min_sdu = 0;
2N/A /* 1518 - 14 (ether header) - 4 (CRC) */
2N/A macp->m_max_sdu = ETHERMTU;
2N/A macp->m_margin = VLAN_TAGSZ;
2N/A
2N/A /*
2N/A * Finally, we're ready to register ourselves with the MAC layer
2N/A * interface; if this succeeds, we're ready to start.
2N/A */
2N/A if (mac_register(macp, &pOdl->mh) != DDI_SUCCESS) {
2N/A mac_free(macp);
2N/A goto attach_failure;
2N/A }
2N/A mac_free(macp);
2N/A
2N/A pLayerPointers->attach_progress |= AMD8111S_ATTACH_MACREGED;
2N/A
2N/A return (DDI_SUCCESS);
2N/A
2N/Aattach_failure:
2N/A (void) amd8111s_unattach(devinfo, pLayerPointers);
2N/A return (DDI_FAILURE);
2N/A
2N/A}
2N/A
2N/A/*
2N/A * detach(9E) -- Detach a device from the system
2N/A *
2N/A * It is called for each device instance when the system is preparing to
2N/A * unload a dynamically unloadable driver.
2N/A * will Do
2N/A * a. check if any driver buffers are held by OS.
2N/A * b. do clean up of all allocated memory if it is not in use by OS.
2N/A * c. un register with GLD
2N/A * d. return DDI_SUCCESS on succes full free & unregister
2N/A * else GLD_FAILURE
2N/A */
2N/Astatic int
2N/Aamd8111s_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
2N/A{
2N/A struct LayerPointers *pLayerPointers;
2N/A
2N/A switch (cmd) {
2N/A case DDI_DETACH:
2N/A break;
2N/A default:
2N/A return (DDI_FAILURE);
2N/A }
2N/A
2N/A /*
2N/A * Get the driver private (struct LayerPointers *) structure
2N/A */
2N/A if ((pLayerPointers = (struct LayerPointers *)ddi_get_driver_private
2N/A (devinfo)) == NULL) {
2N/A return (DDI_FAILURE);
2N/A }
2N/A
2N/A return (amd8111s_unattach(devinfo, pLayerPointers));
2N/A}
2N/A
2N/Astatic int
2N/Aamd8111s_unattach(dev_info_t *devinfo, struct LayerPointers *pLayerPointers)
2N/A{
2N/A struct odl *pOdl = pLayerPointers->pOdl;
2N/A
2N/A if (pLayerPointers->attach_progress & AMD8111S_ATTACH_MACREGED) {
2N/A /* Unregister driver from the GLD interface */
2N/A if (mac_unregister(pOdl->mh) != DDI_SUCCESS) {
2N/A return (DDI_FAILURE);
2N/A }
2N/A }
2N/A
2N/A if (pLayerPointers->attach_progress & AMD8111S_ATTACH_INTRADDED) {
2N/A ddi_remove_intr(devinfo, 0, pOdl->iblock);
2N/A }
2N/A
2N/A if (pLayerPointers->attach_progress & AMD8111S_ATTACH_RESCHED) {
2N/A ddi_remove_softintr(pOdl->drain_id);
2N/A }
2N/A
2N/A if (pLayerPointers->attach_progress & AMD8111S_ATTACH_REGS) {
2N/A /* Stop HW */
2N/A mdlStopChip(pLayerPointers);
2N/A ddi_regs_map_free(&(pOdl->MemBasehandle));
2N/A }
2N/A
2N/A if (pLayerPointers->attach_progress & AMD8111S_ATTACH_RESOURCE) {
2N/A /* Free All memory allocated */
2N/A amd8111s_free_resource(pLayerPointers);
2N/A }
2N/A
2N/A if (pLayerPointers->attach_progress & AMD8111S_ATTACH_PCI) {
2N/A pci_config_teardown(&pOdl->pci_handle);
2N/A mutex_destroy(&pOdl->mdlSendLock);
2N/A mutex_destroy(&pOdl->mdlRcvLock);
2N/A rw_destroy(&pOdl->chip_lock);
2N/A }
2N/A
2N/A kmem_free(pOdl, sizeof (struct odl));
2N/A kmem_free(pLayerPointers, sizeof (struct LayerPointers));
2N/A
2N/A return (DDI_SUCCESS);
2N/A}
2N/A
2N/A/*
2N/A * (GLD Entry Point)GLD will call this entry point perodicaly to
2N/A * get driver statistices.
2N/A */
2N/Astatic int
2N/Aamd8111s_m_stat(void *arg, uint_t stat, uint64_t *val)
2N/A{
2N/A struct LayerPointers *pLayerPointers = arg;
2N/A struct amd8111s_statistics *adapterStat;
2N/A
2N/A adapterStat = &pLayerPointers->pOdl->statistics;
2N/A
2N/A switch (stat) {
2N/A
2N/A /*
2N/A * Current Status
2N/A */
2N/A case MAC_STAT_IFSPEED:
2N/A *val = pLayerPointers->pMdl->Speed * 1000000;
2N/A break;
2N/A
2N/A case ETHER_STAT_LINK_DUPLEX:
2N/A if (pLayerPointers->pMdl->FullDuplex) {
2N/A *val = LINK_DUPLEX_FULL;
2N/A } else {
2N/A *val = LINK_DUPLEX_HALF;
2N/A }
2N/A break;
2N/A
2N/A /*
2N/A * Capabilities
2N/A */
2N/A case ETHER_STAT_CAP_1000FDX:
2N/A *val = 0;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_1000HDX:
2N/A *val = 0;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_100FDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_100HDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_10FDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_10HDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_ASMPAUSE:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_PAUSE:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_CAP_AUTONEG:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_1000FDX:
2N/A *val = 0;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_1000HDX:
2N/A *val = 0;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_100FDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_100HDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_10FDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_10HDX:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_ASMPAUSE:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_PAUSE:
2N/A *val = 1;
2N/A break;
2N/A
2N/A case ETHER_STAT_ADV_CAP_AUTONEG:
2N/A *val = 1;
2N/A break;
2N/A
2N/A /*
2N/A * Rx Counters
2N/A */
2N/A case MAC_STAT_IPACKETS:
2N/A *val = adapterStat->rx_mib_unicst_packets +
2N/A adapterStat->rx_mib_multicst_packets +
2N/A adapterStat->rx_mib_broadcst_packets +
2N/A mdlReadMib(pLayerPointers, RcvUniCastPkts) +
2N/A mdlReadMib(pLayerPointers, RcvMultiCastPkts) +
2N/A mdlReadMib(pLayerPointers, RcvBroadCastPkts);
2N/A break;
2N/A
2N/A case MAC_STAT_RBYTES:
2N/A *val = adapterStat->rx_mib_bytes +
2N/A mdlReadMib(pLayerPointers, RcvOctets);
2N/A break;
2N/A
2N/A case MAC_STAT_MULTIRCV:
2N/A *val = adapterStat->rx_mib_multicst_packets +
2N/A mdlReadMib(pLayerPointers, RcvMultiCastPkts);
2N/A break;
2N/A
2N/A case MAC_STAT_BRDCSTRCV:
2N/A *val = adapterStat->rx_mib_broadcst_packets +
2N/A mdlReadMib(pLayerPointers, RcvBroadCastPkts);
2N/A break;
2N/A
2N/A case MAC_STAT_NORCVBUF:
2N/A *val = adapterStat->rx_allocfail +
2N/A adapterStat->rx_mib_drop_packets +
2N/A mdlReadMib(pLayerPointers, RcvDropPktsRing0);
2N/A break;
2N/A
2N/A case MAC_STAT_IERRORS:
2N/A *val = adapterStat->rx_mib_align_err_packets +
2N/A adapterStat->rx_mib_fcs_err_packets +
2N/A adapterStat->rx_mib_symbol_err_packets +
2N/A mdlReadMib(pLayerPointers, RcvAlignmentErrors) +
2N/A mdlReadMib(pLayerPointers, RcvFCSErrors) +
2N/A mdlReadMib(pLayerPointers, RcvSymbolErrors);
2N/A break;
2N/A
2N/A case ETHER_STAT_ALIGN_ERRORS:
2N/A *val = adapterStat->rx_mib_align_err_packets +
2N/A mdlReadMib(pLayerPointers, RcvAlignmentErrors);
2N/A break;
2N/A
2N/A case ETHER_STAT_FCS_ERRORS:
2N/A *val = adapterStat->rx_mib_fcs_err_packets +
2N/A mdlReadMib(pLayerPointers, RcvFCSErrors);
2N/A break;
2N/A
2N/A /*
2N/A * Tx Counters
2N/A */
2N/A case MAC_STAT_OPACKETS:
2N/A *val = adapterStat->tx_mib_packets +
2N/A mdlReadMib(pLayerPointers, XmtPackets);
2N/A break;
2N/A
2N/A case MAC_STAT_OBYTES:
2N/A *val = adapterStat->tx_mib_bytes +
2N/A mdlReadMib(pLayerPointers, XmtOctets);
2N/A break;
2N/A
2N/A case MAC_STAT_MULTIXMT:
2N/A *val = adapterStat->tx_mib_multicst_packets +
2N/A mdlReadMib(pLayerPointers, XmtMultiCastPkts);
2N/A break;
2N/A
2N/A case MAC_STAT_BRDCSTXMT:
2N/A *val = adapterStat->tx_mib_broadcst_packets +
2N/A mdlReadMib(pLayerPointers, XmtBroadCastPkts);
2N/A break;
2N/A
2N/A case MAC_STAT_NOXMTBUF:
2N/A *val = adapterStat->tx_no_descriptor;
2N/A break;
2N/A
2N/A case MAC_STAT_OERRORS:
2N/A *val = adapterStat->tx_mib_ex_coll_packets +
2N/A mdlReadMib(pLayerPointers, XmtExcessiveCollision);
2N/A break;
2N/A
2N/A case MAC_STAT_COLLISIONS:
2N/A *val = adapterStat->tx_mib_ex_coll_packets +
2N/A mdlReadMib(pLayerPointers, XmtCollisions);
2N/A break;
2N/A
2N/A case ETHER_STAT_FIRST_COLLISIONS:
2N/A *val = adapterStat->tx_mib_one_coll_packets +
2N/A mdlReadMib(pLayerPointers, XmtOneCollision);
2N/A break;
2N/A
2N/A case ETHER_STAT_MULTI_COLLISIONS:
2N/A *val = adapterStat->tx_mib_multi_coll_packets +
2N/A mdlReadMib(pLayerPointers, XmtMultipleCollision);
2N/A break;
2N/A
2N/A case ETHER_STAT_EX_COLLISIONS:
2N/A *val = adapterStat->tx_mib_ex_coll_packets +
2N/A mdlReadMib(pLayerPointers, XmtExcessiveCollision);
2N/A break;
2N/A
2N/A case ETHER_STAT_TX_LATE_COLLISIONS:
2N/A *val = adapterStat->tx_mib_late_coll_packets +
2N/A mdlReadMib(pLayerPointers, XmtLateCollision);
2N/A break;
2N/A
2N/A case ETHER_STAT_DEFER_XMTS:
2N/A *val = adapterStat->tx_mib_defer_trans_packets +
2N/A mdlReadMib(pLayerPointers, XmtDeferredTransmit);
2N/A break;
2N/A
2N/A default:
2N/A return (ENOTSUP);
2N/A }
2N/A return (0);
2N/A}
2N/A
2N/A/*
2N/A * Memory Read Function Used by MDL to set card registers.
2N/A */
2N/Aunsigned char
2N/AREAD_REG8(struct LayerPointers *pLayerPointers, long x)
2N/A{
2N/A return (ddi_get8(pLayerPointers->pOdl->MemBasehandle, (uint8_t *)x));
2N/A}
2N/A
2N/Aint
2N/AREAD_REG16(struct LayerPointers *pLayerPointers, long x)
2N/A{
2N/A return (ddi_get16(pLayerPointers->pOdl->MemBasehandle,
2N/A (uint16_t *)(x)));
2N/A}
2N/A
2N/Along
2N/AREAD_REG32(struct LayerPointers *pLayerPointers, long x)
2N/A{
2N/A return (ddi_get32(pLayerPointers->pOdl->MemBasehandle,
2N/A (uint32_t *)(x)));
2N/A}
2N/A
2N/Avoid
2N/AWRITE_REG8(struct LayerPointers *pLayerPointers, long x, int y)
2N/A{
2N/A ddi_put8(pLayerPointers->pOdl->MemBasehandle, (uint8_t *)(x), y);
2N/A}
2N/A
2N/Avoid
2N/AWRITE_REG16(struct LayerPointers *pLayerPointers, long x, int y)
2N/A{
2N/A ddi_put16(pLayerPointers->pOdl->MemBasehandle, (uint16_t *)(x), y);
2N/A}
2N/A
2N/Avoid
2N/AWRITE_REG32(struct LayerPointers *pLayerPointers, long x, int y)
2N/A{
2N/A ddi_put32(pLayerPointers->pOdl->MemBasehandle, (uint32_t *)(x), y);
2N/A}
2N/A
2N/Avoid
2N/AWRITE_REG64(struct LayerPointers *pLayerPointers, long x, char *y)
2N/A{
2N/A int i;
2N/A for (i = 0; i < 8; i++) {
2N/A WRITE_REG8(pLayerPointers, (x + i), y[i]);
2N/A }
2N/A}
2N/A