Searched refs:pci_phys_hi (Results 1 - 25 of 64) sorted by relevance

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/illumos-gate/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c52 reg.pci_phys_hi = 16 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=16, Func=0 */
67 reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT;
69 reg.pci_phys_hi = 17 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=17, Func=0 */
79 reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT;
81 reg.pci_phys_hi = 21 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=21, Func=0 */
88 reg.pci_phys_hi = 22 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=22, Func=0 */
95 reg.pci_phys_hi = 0; /* Bus=0, Dev=0, Func=0 */
105 reg.pci_phys_hi += 1 << PCI_REG_DEV_SHIFT;
/illumos-gate/usr/src/uts/intel/io/pciex/
H A Dpcie_nvidia.c228 regs[0].pci_phys_hi = devloc;
234 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B |
243 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B |
/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_util.c148 uint32_t phys_hi = rp->pci_phys_hi;
152 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
182 uint32_t assign_type = assign_p->pci_phys_hi & PCI_REG_ADDR_M;
183 uint32_t assign_addr = PCI_REG_BDFR_G(assign_p->pci_phys_hi);
196 rp->pci_phys_hi ^= PCI_ADDR_MEM64 ^ PCI_ADDR_MEM32;
202 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
216 uint32_t space_type = PCI_REG_ADDR_G(px_rp->pci_phys_hi);
228 reg_begin += px_rp->pci_phys_hi << 4;
351 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
354 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi), fun
[all...]
/illumos-gate/usr/src/uts/sun4/io/efcode/
H A Dfcpci.c563 p.pci_phys_hi = fc_cell2uint(fc_arg(cp, 1));
850 p.pci_phys_hi = fc_cell2uint(fc_arg(cp, 0));
858 if ((p.pci_phys_hi & PCI_ADDR_MASK) != PCI_ADDR_CONFIG) {
860 "invalid config addr: %x\n", p.pci_phys_hi);
869 reg = (p.pci_phys_hi & PCI_REG_REG_M) |
870 (((p.pci_phys_hi & PCI_REG_EXTREG_M) >> PCI_REG_EXTREG_SHIFT) << 8);
872 p.pci_phys_hi &= PCI_BDF_bits;
982 p.pci_phys_hi = fc_cell2uint(fc_arg(cp, 0));
990 if ((p.pci_phys_hi & PCI_ADDR_MASK) != PCI_ADDR_CONFIG) {
992 "invalid config addr: %x\n", p.pci_phys_hi);
[all...]
/illumos-gate/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_util.c144 register uint32_t phys_hi = rp->pci_phys_hi;
150 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
171 if ((assign_p->pci_phys_hi & mask) == phys_addr) {
179 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
194 uint32_t space_type = PCI_REG_ADDR_G(pcmu_rp->pci_phys_hi);
205 reg_begin += pcmu_rp->pci_phys_hi;
316 func = PCI_REG_FUNC_G(pcmu_rp[0].pci_phys_hi);
319 PCI_REG_DEV_G(pcmu_rp[0].pci_phys_hi), func);
322 PCI_REG_DEV_G(pcmu_rp[0].pci_phys_hi));
/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c161 register uint32_t phys_hi = rp->pci_phys_hi;
164 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
184 uint32_t assign_type = assign_p->pci_phys_hi & PCI_REG_ADDR_M;
185 uint32_t assign_addr = PCI_REG_BDFR_G(assign_p->pci_phys_hi);
196 rp->pci_phys_hi ^= PCI_ADDR_MEM64 ^ PCI_ADDR_MEM32;
202 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low,
217 uint32_t space_type = PCI_REG_ADDR_G(pci_rp->pci_phys_hi);
227 reg_begin += pci_rp->pci_phys_hi;
348 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
351 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi), fun
[all...]
/illumos-gate/usr/src/uts/common/io/
H A Dbusra.c1038 switch (PCI_REG_ADDR_G(regs[i].pci_phys_hi)) {
1043 (regs[i].pci_phys_hi & PCI_REG_PF_M) ?
1054 (regs[i].pci_phys_hi & PCI_REG_PF_M) ?
1071 PCI_REG_ADDR_G(regs[i].pci_phys_hi));
1225 if (avail_p->pci_phys_hi == -1u)
1228 switch (PCI_REG_ADDR_G(avail_p->pci_phys_hi)) {
1232 (avail_p->pci_phys_hi & PCI_REG_PF_M) ?
1254 i, avail_p->pci_phys_hi);
1356 if (type == (regs[i].pci_phys_hi & PCI_ADDR_TYPE_MASK)) {
1386 newregs[j].pci_phys_hi
[all...]
H A Dpci_intr_lib.c841 addr_space = rp->pci_phys_hi & PCI_ADDR_MASK;
842 offset = PCI_REG_REG_G(rp->pci_phys_hi);
890 addr_space = rp->pci_phys_hi & PCI_ADDR_MASK;
891 offset = PCI_REG_REG_G(rp->pci_phys_hi);
/illumos-gate/usr/src/uts/sun4/io/
H A Dpcicfg.c1514 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) ==
1520 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) ==
1984 offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
1986 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
2129 offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
2132 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
2162 reg[i].pci_phys_hi ^=
2299 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) {
2651 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) {
2764 switch (PCI_REG_ADDR_G(pci_ap[i].pci_phys_hi)) {
[all...]
/illumos-gate/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c348 rangep[i].ebus_phys_low, rangep[i].pci_phys_hi,
465 pci_reg.pci_phys_hi |= PCI_RELOCAT_B;
469 pci_reg.pci_phys_hi,
516 rp->pci_phys_hi =
517 rangep->pci_phys_hi;
531 rangep->pci_phys_hi,
973 if (PCI_REG_REG_G(prp->pci_phys_hi) == er[0].ebus_phys_hi) {
985 er[0].pci_phys_hi = prp->pci_phys_hi;
997 if (PCI_REG_REG_G(prp->pci_phys_hi)
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/illumos-gate/usr/src/uts/sparc/io/pciex/
H A Dpcieb_sparc.c105 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
383 if ((reg_spec[rnum].pci_phys_hi & PCI_ADDR_MASK) ==
395 if ((addr_spec[anum].pci_phys_hi & PCI_ADDR_MASK) ==
408 reg_spec[rnum].pci_phys_hi = (addr_spec[anum].pci_phys_hi &
/illumos-gate/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1415 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) ==
1420 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) ==
1425 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) ==
1880 offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
1882 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
1885 if (reg[i].pci_phys_hi & PCI_REG_PF_M) {
1900 reg[i].pci_phys_hi |= PCI_REG_REL_M;
1906 if (reg[i].pci_phys_hi & PCI_REG_PF_M) {
1922 reg[i].pci_phys_hi |= PCI_REG_REL_M;
1936 reg[i].pci_phys_hi |
[all...]
/illumos-gate/usr/src/uts/i86pc/io/gfx_private/
H A Dgfxp_pci.c101 *bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi);
102 *dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
103 *func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
/illumos-gate/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c892 offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
893 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
1040 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
1051 range.par_phys_hi = reg[i].pci_phys_hi |
2092 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) {
2103 PCI_REG_REG_G(pci_rp[i].pci_phys_hi));
2121 PCI_REG_REG_G(pci_rp[i].pci_phys_hi));
2135 PCI_REG_REG_G(pci_rp[i].pci_phys_hi));
2280 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) {
2287 PCI_REG_REG_G(assigned[i].pci_phys_hi));
[all...]
H A Dcardbus_hp.c891 if (pci_rp->pci_phys_hi == 0)
895 bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi);
896 device = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
897 function = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
991 if (pci_rp->pci_phys_hi == 0)
994 bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi);
999 device = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
1000 func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/oce/
H A Doce_hw.c204 dev->pci_bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi);
205 dev->pci_device = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
206 dev->pci_function = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
/illumos-gate/usr/src/uts/i86pc/io/pci/
H A Dpci.c413 space = pci_rp->pci_phys_hi & PCI_REG_ADDR_M;
478 cfp->c_busnum = PCI_REG_BUS_G(pci_rp->pci_phys_hi);
479 cfp->c_devnum = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
480 cfp->c_funcnum = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dsbbcvar.h71 uint32_t pci_phys_hi; /* Parent hi rng addr */ member in struct:sbbc_pci_rangespec
/illumos-gate/usr/src/uts/sun4u/montecarlo/sys/
H A Dacebus.h115 uint32_t pci_phys_hi; /* Parent hi rng addr */ member in struct:ebus_pci_rangespec
/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dnhm_pci_cfg.c55 reg.pci_phys_hi = ((SOCKET_BUS(i))
/illumos-gate/usr/src/uts/intel/io/pci/
H A Dpci_boot.c2377 regs[0].pci_phys_hi = devloc;
2457 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc |
2461 assigned[nasgn].pci_phys_hi =
2462 PCI_RELOCAT_B | regs[nreg].pci_phys_hi;
2574 regs[nreg].pci_phys_hi =
2575 assigned[nasgn].pci_phys_hi = phys_hi;
2576 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2672 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2673 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2697 regs[nreg].pci_phys_hi
[all...]
/illumos-gate/usr/src/uts/sun4u/io/
H A Dpmubus.c614 pci_regp->pci_phys_hi = rangep->rng_parent_hi;
621 if (pci_regp->pci_phys_hi == pmubusp->pmubus_regp->pci_phys_hi) {
/illumos-gate/usr/src/uts/i86pc/io/psm/
H A Dpsm_common.c244 *bus = (int)PCI_REG_BUS_G(pci_rp->pci_phys_hi);
246 *device = (int)PCI_REG_DEV_G(pci_rp->pci_phys_hi);
248 *func = (int)PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
/illumos-gate/usr/src/uts/common/os/
H A Dpcifm.c456 phys_hi = pci_rp->pci_phys_hi;
1221 * on pci_phys_hi of the config space entry in reg property.
1230 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi) &&
1233 (drv_regp[rn].pci_phys_hi & (PCI_REG_BUS_M |
1253 if ((drv_regp[rn].pci_phys_hi & PCI_RELOCAT_B) &&
1256 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi)) &&
1281 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi)) &&
/illumos-gate/usr/src/uts/i86pc/io/pciex/
H A Dnpe.c487 space = pci_rp->pci_phys_hi & PCI_REG_ADDR_M;
579 cfp->c_busnum = PCI_REG_BUS_G(pci_rp->pci_phys_hi);
580 cfp->c_devnum = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
581 cfp->c_funcnum = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);

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