/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2015 Joyent, Inc.
*/
#include <sys/sysmacros.h>
#include <sys/pci_impl.h>
#include <sys/pcie_impl.h>
#include <sys/bootconf.h>
#include <sys/pci_cfgacc.h>
#include <sys/pci_cfgspace.h>
#include <sys/pci_cfgspace_impl.h>
#include "../../../../common/pci/pci_strings.h"
#include <sys/iommulib.h>
#include <sys/devcache.h>
#include <sys/pci_cfgacc_x86.h>
#define CONFIG_INFO 0
/* round down to nearest power of two */
{ \
int i = 0; \
while (align >>= 1) \
i ++; \
align = 1 << i; \
} \
/* for is_vga and list_is_vga_only */
enum io_mem {
IO,
};
/* See AMD-8111 Datasheet Rev 3.03, Page 149: */
struct pci_fixundo {
};
struct pci_devfunc {
};
extern int apic_nvidia_io_max;
extern int pseudo_isa;
extern int pci_bios_maxbus;
int pci_boot_debug = 0;
extern struct memlist *find_bus_res(int, int);
extern volatile int acpi_resource_discovery;
extern uint64_t mcfg_mem_base;
/*
* Module prototypes
*/
ushort_t, int);
ushort_t);
static void add_bus_range_prop(int);
static void add_bus_slot_names_prop(int);
static void add_ranges_prop(int, int);
static void add_bus_available_prop(int);
static void alloc_res_array();
struct memlist *remove_list);
static void pci_scan_bbn(void);
static int pci_unitaddr_cache_valid(void);
static int pci_bus_unitaddr(int);
static void pci_unitaddr_cache_create(void);
static void pci_cache_free_list(nvf_handle_t);
extern int pci_slot_names_prop(int, char *, int);
/* set non-zero to force PCI peer-bus renumbering */
int pci_bus_always_renumber = 0;
/*
* used to register ISA resource usage which must not be made
* "available" from other PCI node' resource maps
*/
static struct {
} isa_res;
/*
* PCI unit-address cache management
*/
"/etc/devices/pci_unitaddr_persistent", /* path to cache */
pci_cache_unpack_nvlist, /* read in nvlist form */
pci_cache_pack_nvlist, /* convert to nvlist form */
pci_cache_free_list, /* free data list */
NULL /* write complete callback */
};
typedef struct {
int pua_index;
int pua_addr;
} pua_node_t;
int pua_cache_valid = 0;
/*ARGSUSED*/
static ACPI_STATUS
{
int busnum;
/*
* Use AcpiGetObjectInfo() to find the device _HID
* If not a PCI root-bus, ignore this device and continue
* the walk
*/
return (AE_OK);
return (AE_OK);
}
sizeof (PCI_ROOT_HID_STRING)) &&
sizeof (PCI_EXPRESS_ROOT_HID_STRING))) {
return (AE_OK);
}
/*
* XXX: ancient Big Bear broken _BBN will result in two
* bus 0 _BBNs being found, so we need to handle duplicate
* bus 0 gracefully. However, broken _BBN does not
* hide a childless root-bridge so no need to work-around it
* here
*/
/*
* Ignore invalid _BBN return values here (rather
* than panic) and emit a warning; something else
* may suffer failure as a result of the broken BIOS.
*/
"pci_process_acpi_device: invalid _BBN 0x%x\n",
busnum);
return (AE_CTRL_DEPTH);
}
/* PCI with valid _BBN */
return (AE_CTRL_DEPTH);
}
/* PCI and no _BBN, continue walk */
return (AE_OK);
}
/*
* Scan the ACPI namespace for all top-level instances of _BBN
* in order to discover childless root-bridges (which enumeration
* may not find; root-bridges are inferred by the existence of
* children). This scan should find all root-bridges that have
* been enumerated, and any childless root-bridges not enumerated.
* Root-bridge for bus 0 may not have a _BBN object.
*/
static void
{
void *rv;
}
static void
pci_unitaddr_cache_init(void)
{
(void) nvf_read_file(puafd_handle);
}
/*
* Format of /etc/devices/pci_unitaddr_persistent:
*
* The persistent record of unit-address assignments contains
* of the "index value" of the PCI root-bus and the value is
* the assigned unit-address.
*
* The "index value" is simply the zero-based index of the PCI
* root-buses ordered by physical bus number; first PCI bus is 0,
* second is 1, and so on.
*/
/*ARGSUSED*/
static int
{
long index;
/* name of nvpair is index value */
continue;
continue;
}
pua_cache_valid = 1;
return (DDI_SUCCESS);
}
static int
{
int rval;
if (rval != DDI_SUCCESS) {
nvf_error("%s: nvlist alloc error %d\n",
return (DDI_FAILURE);
}
if (rval != DDI_SUCCESS)
goto error;
if (rval != DDI_SUCCESS)
goto error;
}
if (rval != DDI_SUCCESS)
goto error;
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
static void
{
}
}
static int
pci_unitaddr_cache_valid(void)
{
/* read only, no need for rw lock */
return (pua_cache_valid);
}
static int
{
int addr;
break;
}
}
return (addr);
}
static void
{
int i, index;
index = 0;
for (i = 0; i <= pci_bios_maxbus; i++) {
/* skip non-root (peer) PCI busses */
continue;
}
(void) nvf_mark_dirty(puafd_handle);
}
/*
* Enumerate all PCI devices
*/
void
pci_setup_tree(void)
{
for (i = 0; i <= pci_bios_maxbus; i++) {
pci_bus_res[i].sub_bus = i;
}
/*
* Now enumerate peer busses
*
* We loop till pci_bios_maxbus. On most systems, there is
* one more bus at the high end, which implements the ISA
* compatibility bus. We don't care about that.
*
* Note: In the old (bootconf) enumeration, the peer bus
* address did not use the bus number, and there were
* too many peer busses created. The root_bus_addr is
* used to maintain the old peer bus address assignment.
* However, we stop enumerating phantom peers with no
* device below.
*/
for (i = 1; i <= pci_bios_maxbus; i++) {
}
/* add slot-names property for named pci hot-plug slots */
}
}
/*
* >0 = present, 0 = not present, <0 = error
*/
static int
{
int rv;
/* no dip means no _BBN */
return (0);
case AE_OK:
rv = 1;
break;
case AE_NOT_FOUND:
rv = 0;
break;
default:
break;
}
}
return (rv);
}
/*
* Return non-zero if any PCI bus in the system has an associated
* _BBN object, 0 otherwise.
*/
static int
pci_roots_have_bbn(void)
{
int i;
/*
* Scan the PCI busses and look for at least 1 _BBN
*/
for (i = 0; i <= pci_bios_maxbus; i++) {
/* skip non-root (peer) PCI busses */
continue;
if (pci_bbn_present(i) > 0)
return (1);
}
return (0);
}
/*
* return non-zero if the machine is one on which we renumber
* the internal pci unit-addresses
*/
static int
{
return (1);
/* get the FADT */
return (0);
/* compare OEM Table ID to "SUNm31" */
return (0);
else
return (1);
}
/*
* Initial enumeration of the physical PCI bus hierarchy can
* leave 'gaps' in the order of peer PCI bus unit-addresses.
* Systems with more than one peer PCI bus *must* have an ACPI
* _BBN object associated with each peer bus; use the presence
* of this object to remove gaps in the numbering of the peer
* PCI bus unit-addresses - only peer busses with an associated
* _BBN are counted.
*/
static void
pci_renumber_root_busses(void)
{
int pci_regs[] = {0, 0, 0};
int i, root_addr = 0;
/*
* Currently, we only enable the re-numbering on specific
* Sun machines; this is a work-around for the more complicated
* issue of upgrade changing physical device paths
*/
if (!pci_bus_renumber())
return;
/*
* If we find no _BBN objects at all, we either don't need
* to do anything or can't do anything anyway
*/
if (!pci_roots_have_bbn())
return;
for (i = 0; i <= pci_bios_maxbus; i++) {
/* skip non-root (peer) PCI busses */
continue;
if (pci_bbn_present(i) < 1) {
continue;
}
/* update reg property for node */
}
root_addr++;
}
}
void
{
(void) memlist_insert(
}
/*
* Remove the resources which are already used by devices under a subtractive
* bridge from the bus's resources lists, because they're not available, and
* shouldn't be allocated to other buses. This is necessary because tracking
* resources for subtractive bridges is not complete. (Subtractive bridges only
* track some of their claimed resources, not "the rest of the address space" as
* they should, so that allocation to peer non-subtractive PPBs is easier. We
* need a fully-capable global resource allocator).
*/
static void
{
int i, j;
for (i = 0; i <= pci_bios_maxbus; i++) {
if (pci_bus_res[i].subtractive) {
/* remove used io ports */
while (list) {
for (j = 0; j <= pci_bios_maxbus; j++)
(void) memlist_remove(
&pci_bus_res[j].io_avail,
}
/* remove used mem resource */
while (list) {
for (j = 0; j <= pci_bios_maxbus; j++) {
(void) memlist_remove(
&pci_bus_res[j].mem_avail,
(void) memlist_remove(
&pci_bus_res[j].pmem_avail,
}
}
/* remove used prefetchable mem resource */
while (list) {
for (j = 0; j <= pci_bios_maxbus; j++) {
(void) memlist_remove(
&pci_bus_res[j].pmem_avail,
(void) memlist_remove(
&pci_bus_res[j].mem_avail,
}
}
}
}
}
/*
* Set up (or complete the setup of) the bus_avail resource list
*/
static void
{
return;
/*
* Set up bus_avail if not already filled in by populate_bus_res()
*/
}
/*
* Remove resources from parent bus node if this is not a
* root bus.
*/
}
/* remove self from bus_avail */;
}
static uint64_t
{
/*
* Skip root(peer) buses in multiple-root-bus systems when
* ACPI resource discovery was not successfully done.
*/
return (0);
break;
break; /* root bus already */
}
if (addr) {
/* free the old resource */
/* add the new resource */
}
}
return (addr);
}
static uint64_t
{
/*
* Skip root(peer) buses in multiple-root-bus systems when
* ACPI resource discovery was not successfully done.
*/
return (0);
break;
break; /* root bus already */
}
if (addr) {
/* free the old resource */
/* add the new resource */
}
}
return (addr);
}
/*
* given a cap_id, return its cap_id location in config space
*/
static int
{
/*
* Need to check the Status register for ECP support first.
* Also please note that for type 1 devices, the
* offset could change. Should support type 1 next.
*/
if (!(status & PCI_STAT_CAP)) {
return (-1);
}
/* Walk the list of capabilities */
break;
}
}
return (location);
}
/*
* Does this resource element live in the legacy VGA range?
*/
int
{
return (1);
} else {
return (1);
}
return (0);
}
/*
* Does this entire resource list consist only of legacy VGA resources?
*/
int
{
do {
return (0);
return (1);
}
/*
* Assign valid resources to unconfigured pci(e) bridges. We are trying
* to reprogram the bridge when its
* i) SECBUS == SUBBUS ||
* ii) IOBASE > IOLIM ||
* iii) MEMBASE > MEMLIM
* This must be done after one full pass through the PCI tree to collect
* all BIOS-configured resources, so that we know what resources are
* free and available to assign to the unconfigured PPBs.
*/
static void
{
/* skip root (peer) PCI busses */
return;
/* skip subtractive PPB when prog_sub is not TRUE */
return;
/* some entries may be empty due to discontiguous bus numbering */
return;
return;
/*
* If pcie bridge, check to see if link is enabled
*/
if (cap_ptr != -1) {
if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
"!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
return;
}
}
/*
* If we have a Cardbus bridge, but no bus space
*/
/* normally there are 2 buses under a cardbus bridge */
/*
* Try to find and allocate a bus-range starting at subbus+1
* from the parent of the PPB.
*/
break; /* find bus range resource at parent */
}
if (range != 0) {
}
}
/*
* Calculate required IO size and alignment
* If bus io_size is zero, we are going to assign 512 bytes per bus,
* otherwise, we'll choose the maximum value of such calculation and
* bus io_size. The size needs to be 4K aligned.
*
* We calculate alignment as the largest power of two less than the
* the sum of all children's IO size requirements, because this will
* align to the size of the largest child request within that size
* (which is always a power of two).
*/
/*
* Calculate required MEM size and alignment
* If bus mem_size is zero, we are going to assign 1M bytes per bus,
* otherwise, we'll choose the maximum value of such calculation and
* bus mem_size. The size needs to be 1M aligned.
*
* For the alignment, refer to the I/O comment above.
*/
}
/* Subtractive bridge */
/*
* We program an arbitrary amount of I/O and memory resource
* for the subtractive bridge so that child dynamic-resource-
* allocating devices (such as Cardbus bridges) have a chance
* of success. Until we have full-tree resource rebalancing,
* dynamic resource allocation (thru busra) only looks at the
* parent bridge, so all PPBs must have some allocatable
* resource. For non-subtractive bridges, the resources come
* bridges often don't program those (since they don't need to).
* If we put all the remaining resources on the subtractive
* bridge, then peer non-subtractive bridges can't allocate
* more space (even though this is probably most correct).
* If we put the resources only on the parent, then allocations
* from children of subtractive bridges will fail without
* special-case code for bypassing the subtractive bridge.
* This solution is the middle-ground temporary solution until
* we have fully-capable resource allocation.
*/
/*
* Add an arbitrary I/O resource to the subtractive PPB
*/
io_align);
if (addr) {
" ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
}
}
/*
* Add an arbitrary memory resource to the subtractive PPB
*/
if (addr) {
"subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
}
}
goto cmd_enable;
}
/*
* Check to see if we need to reprogram I/O space, either because the
* parent bus needed reprogramming and so do we, or because I/O space is
*/
/* Form list of all resources passed (avail + used) */
(!(cmd_reg & PCI_COMM_IO))) &&
}
/* rechoose old io ports info */
io_base = 0;
do {
continue;
if (!io_base) {
io_base =
} else {
io_limit) {
(list->ml_address +
}
}
/* 4K aligned */
} else {
/* get new io ports from parent bus */
io_align);
if (addr) {
}
}
/* reprogram PPB regs */
" ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
}
}
/*
* Check memory space as we did I/O space.
*/
(!(cmd_reg & PCI_COMM_MAE))) &&
}
/* rechoose old mem resource */
mem_base = 0;
do {
continue;
if (mem_base == 0) {
} else {
mem_limit) {
(list->ml_address +
}
}
} else {
/* get new mem resource from parent bus */
if (addr) {
}
}
/* reprogram PPB MEM regs */
/*
* Disable PMEM window by setting base > limit.
* We currently don't reprogram the PMEM like we've
* done for I/O and MEM. (Devices that support prefetch
* can use non-prefetch MEM.) Anyway, if the MEM access
* bit is initially disabled by BIOS, we disable the
* PMEM window manually by setting PMEM base > PMEM
* limit here, in case there are incorrect values in
* them from BIOS, so that we won't get in trouble once
* the MEM access bit is enabled at the end of this
* function.
*/
if (!(cmd_reg & PCI_COMM_MAE)) {
0xfff0);
0x0);
0xffffffff);
0x0);
}
" ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
}
}
}
void
pci_reprogram(void)
{
char *onoff;
int bus;
/*
* Scan ACPI namespace for _BBN objects, make sure that
* childless root-bridges appear in devinfo tree
*/
pci_scan_bbn();
/*
* Fix-up unit-address assignments if cache is available
*/
if (pci_unitaddr_cache_valid()) {
int pci_regs[] = {0, 0, 0};
int new_addr;
int index = 0;
/* skip non-root (peer) PCI busses */
continue;
/* update reg property for node */
(void) ndi_prop_update_int_array(
}
index++;
}
} else {
/* perform legacy processing */
}
/*
* Do root-bus resource discovery
*/
/* skip non-root (peer) PCI busses */
continue;
/*
* 1. find resources associated with this root bus
*/
/*
* 2. Remove used PCI and ISA resources from bus resource map
*/
/*
* 3. Exclude <1M address range here in case below reserved
* ranges for BIOS data area, ROM area etc are wrongly reported
* in ACPI resource producer entries for PCI root bus.
* 00000000 - 000003FF RAM
* 00000400 - 000004FF BIOS data area
* 00000500 - 0009FFFF RAM
* 000A0000 - 000BFFFF VGA RAM
* 000C0000 - 000FFFFF ROM area
*/
0, 0x100000);
}
for (i = 0; i <= pci_bios_maxbus; i++) {
/* setup bus range resource on each bus */
setup_bus_res(i);
}
pci_reconfig = 0;
}
}
/* reprogram the non-subtractive PPB */
if (pci_reconfig)
for (i = 0; i <= pci_bios_maxbus; i++)
fix_ppb_res(i, B_FALSE);
for (i = 0; i <= pci_bios_maxbus; i++) {
/* configure devices not configured by BIOS */
if (pci_reconfig) {
/*
* Reprogram the subtractive PPB. At this time, all its
* siblings should have got their resources already.
*/
if (pci_bus_res[i].subtractive)
fix_ppb_res(i, B_TRUE);
}
}
/* All dev programmed, so we can create available prop */
for (i = 0; i <= pci_bios_maxbus; i++)
}
/*
* populate bus resources
*/
static void
{
/* scan BIOS structures */
/*
* attempt to initialize sub_bus from the largest range-end
* in the bus_avail list
*/
int current;
}
}
if (bus == 0) {
/*
* Special treatment of bus 0:
* pcimem from boot and make I/O space the entire range
* starting at 0x100.
*/
pci_bus_res[0].mem_avail =
/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
}
/*
* Create 'ranges' property here before any resources are
* removed from the resource lists
*/
add_ranges_prop(bus, 0);
}
/*
* Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
*/
static void
{
int pci_regs[] = {0, 0, 0};
num_root_bus++;
"#address-cells", 3);
"#size-cells", 2);
/*
* If system has PCIe bus, then create different properties
*/
"device_type", "pci");
(void) ndi_devi_bind_driver(dip, 0);
}
/*
* For any fixed configuration (often compatability) pci devices
* and those with their own expansion rom, create device nodes
* to hold the already configured device details.
*/
void
{
if (config_op == CONFIG_NEW) {
} else if (config_op == CONFIG_FIX) {
} else
if (config_op == CONFIG_NEW) {
while (devlist) {
/* reprogram device(s) */
}
}
return;
}
nfunc = 1;
/* no function at this address */
continue;
}
if (header == 0xff) {
continue; /* illegal value */
}
/*
* according to some mail from Microsoft posted
* to the pci-drivers alias, their only requirement
* for a multifunction device is for the 1st
* function to have to PCI_HEADER_MULTI bit set.
*/
nfunc = 8;
}
if (config_op == CONFIG_FIX ||
config_op == CONFIG_INFO) {
/*
* Create the node, unconditionally, on the
* first pass only. It may still need
* resource assignment, which will be
* done on the second, CONFIG_NEW, pass.
*/
}
}
}
/* percolate bus used resources up through parents to root */
if (config_op == CONFIG_INFO) {
int par_bus;
}
}
}
static int
{
static char *pciide_str;
if (prop_exist == -1) {
&pciide_str) == DDI_SUCCESS);
}
if (!prop_exist)
return (0);
/* compare property value against various forms of compatible */
if (subvenid) {
return (1);
return (1);
return (1);
}
return (1);
return (1);
return (0);
}
static int
{
} *entry;
/* XXX SATA and other devices: need a way to add dynamically */
{0x1095, 0x3112},
{0x1095, 0x3114},
{0x1095, 0x3512},
{0x1095, 0x680}, /* Sil0680 */
{0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */
{0, 0}
};
if (basecl != PCI_CLASS_MASS)
return (0);
if (subcl == PCI_MASS_IDE) {
return (1);
}
return (1);
return (0);
}
return (1);
entry++;
}
return (0);
}
static int
{
0x000100,
0x030000,
0x030001
};
for (i = 0; i < nclasses; i++) {
if (classcode == disp_classes[i])
return (1);
}
return (0);
}
static void
{
/*
* Adding an item to this list means that we must turn its NMIENABLE
* bit back on at a later time.
*/
/* add to the undo list in LIFO order */
}
void
add_pci_fixes(void)
{
int i;
for (i = 0; i <= pci_bios_maxbus; i++) {
/*
* For each bus, apply needed fixes to the appropriate devices.
* This must be done before the main enumeration loop because
* some fixes must be applied to devices normally encountered
* later in the pci scan (e.g. if a fix to device 7 must be
* applied before scanning device 6, applying fixes in the
* normal enumeration loop would obviously be too late).
*/
}
}
void
undo_pci_fixes(void)
{
/*
* All fixes in the undo list are performed unconditionally. Future
* fixes may require selective undo.
*/
}
}
static void
{
/*
* The NMIONERR bit is turned back on to allow the SMM BIOS
* to handle more critical PCI errors (e.g. PERR#).
*/
}
static void
{
if ((val8 & AMD8111_ENABLENMI) == 0)
return;
/*
* We reset NMIONERR in the LPC because master-abort on the PCI
* bridge side of the 8111 will cause NMI, which might cause SMI,
* which sometimes prevents all devices from being enumerated.
*/
val8 &= ~AMD8111_ENABLENMI;
}
static void
{
if (!(status & PCI_STAT_CAP))
return; /* No capabilities list */
if (header == PCI_HEADER_CARDBUS)
else
/*
* Walk the capabilities list searching for a PM entry.
*/
if (cap_id == PCI_CAP_ID_PM) {
pmcsr &= ~(PCI_PMCSR_STATE_MASK);
break;
}
}
}
static void
{
int pciex = 0;
switch (header & PCI_HEADER_TYPE_M) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_CARDBUS:
/* Record the # of cardbus bridges found on the bus */
if (config_op == CONFIG_INFO)
break;
default:
subvenid = 0;
subdevid = 0;
break;
}
if (config_op == CONFIG_FIX) {
}
return;
}
/* XXX should be use generic names? derive from class? */
/* figure out if this is pci-ide */
if (is_display(classcode))
else if (subvenid != 0)
else
/* make sure parent bus dip has been created */
DEVI_SID_NODEID, &dip);
pciex = 1;
/*
* Record BAD AMD bridges which don't support MMIO config access.
*/
if ((basecl == PCI_CLASS_BRIDGE) &&
(subcl == PCI_BRIDGE_PCI)) {
}
}
/*
* Only populate bus_t if this device is sitting under a PCIE root
* complex. Some particular machines have both a PCIE root complex and
* a PCI hostbridge, in which case only devices under the PCIE root
* complex will have their bus_t populated.
*/
}
/* add properties */
"class-code", classcode);
if (func == 0)
else
"unit-address", unitaddr);
/* add device_type for display nodes */
if (is_display(classcode)) {
"device_type", "display");
}
/* add special stuff for header type */
if (subvenid != 0) {
"subsystem-id", subdevid);
"subsystem-vendor-id", subvenid);
}
if (!pciex)
"min-grant", mingrant);
if (!pciex)
"max-latency", maxlatency);
}
/* interrupt, record if not 0 */
if (intr != 0)
"interrupts", intr);
/*
* Add support for 133 mhz pci eventually
*/
"fast-back-to-back");
"66mhz-capable");
if (status & PCI_STAT_UDF)
"udf-supported");
if (pciex && slot_valid) {
"physical-slot#", slot_num);
if (!is_pci_bridge)
}
/* Set the device PM state to D0 */
else {
/*
* Record the non-PPB devices on the bus for possible
* reprogramming at 2nd bus enumeration.
* Note: PPB reprogramming is done in fix_ppb_res()
*/
}
}
(func == 0)) {
/* each LPC bridge has an integrated IOAPIC */
}
if (pciex && is_pci_bridge)
(char *)"PCIe-PCI bridge");
else
/*
* See if this device is a controller that advertises
* itself to be a standard ATA task file controller, or one that
* has been hard coded.
*
* If it is, check if any other higher precedence driver listed in
* driver_aliases will claim the node by calling
* ddi_compatibile_driver_major. If so, clear pciide and do not
* create a pci-ide node or any other special handling.
*
* If another driver does not bind, set the node name to pci-ide
* and then let the special pci-ide handling for registers and
* child pci-ide nodes proceed below.
*/
pciide = 1;
}
}
(void) ndi_devi_bind_driver(dip, 0);
/* special handling for pci-ide */
if (pciide) {
/*
* Create properties specified by P1275 Working Group
* Proposal #414 Version 1
*/
"device_type", "pci-ide");
"#address-cells", 1);
"#size-cells", 0);
/* allocate two child nodes */
"reg", 0);
(void) ndi_devi_bind_driver(cdip, 0);
"reg", 1);
(void) ndi_devi_bind_driver(cdip, 0);
reprogram = 0; /* don't reprogram pci-ide bridge */
}
if (is_display(classcode)) {
}
/* special handling for isa */
/* add device_type */
"device_type", "isa");
}
}
/*
* Some vendors do not use unique subsystem IDs in their products, which
* makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate.
* Allow for these compatible forms to be excluded on a per-device basis.
*/
/*ARGSUSED*/
static boolean_t
{
/* Nvidia display adapters */
return (B_TRUE);
return (B_FALSE);
}
/*
* Set the compatible property to a value compliant with
* rev 2.1 of the IEEE1275 PCI binding.
* (Also used for PCI-Express devices).
*
* pciVVVV,DDDD.SSSS.ssss.RR (0)
* pciVVVV,DDDD.SSSS.ssss (1)
* pciSSSS,ssss (2)
* pciVVVV,DDDD.RR (3)
* pciVVVV,DDDD (4)
* pciclass,CCSSPP (5)
* pciclass,CCSS (6)
*
* The Subsystem (SSSS) forms are not inserted if
* subsystem-vendor-id is 0.
*
* NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
* property 2 is not created as per "1275 bindings for PCI Express Interconnect"
*
* Set with setprop and \x00 between each
* to generate the encoded string array form.
*/
void
int pciex)
{
int i = 0;
if (pciex) {
if (subvenid) {
}
(classcode >> 8));
}
if (subvenid) {
subdevid);
}
}
"compatible", compat, i);
}
/*
* Adjust the reg properties for a dual channel PCI-IDE device.
*
* NOTE: don't do anything that changes the order of the hard-decodes
* and programmed BARs. The kernel driver depends on these values
* being in this order regardless of whether they're for a 'native'
* mode BAR or not.
*/
/*
* config info for pci-ide devices
*/
static struct {
} pciide_bar[] = {
{ 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */
{ 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */
{ 0x04, 0, 0x170, 8 }, /* secondary lower BAR */
{ 0x04, 2, 0x376, 1 } /* secondary upper BAR */
};
static int
{
int hard_decode = 0;
/*
* Adjust the base and len for the BARs of the PCI-IDE
* device's primary and secondary controllers. The first
* two BARs are for the primary controller and the next
* two BARs are for the secondary controller. The fifth
* and sixth bars are never adjusted.
*/
} else {
hard_decode = 1;
}
}
/*
* if either base or len is zero make certain both are zero
*/
*basep = 0;
*lenp = 0;
hard_decode = 0;
}
return (hard_decode);
}
/*
* Add the "reg" and "assigned-addresses" property
*/
static int
{
nasgn = 0;
switch (header) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_PPB:
break;
case PCI_HEADER_CARDBUS:
reprogram = 1;
break;
default:
max_basereg = 0;
break;
}
/*
* Create the register property by saving the current
* value of the base register. Write 0xffffffff to the
* base register. Read the value back to determine the
* required size of the address space. Restore the base
* register contents.
*
* Do not disable I/O and memory access for bridges; this
* has the side-effect of making the bridge transparent to
* secondary-bus activity (see sections 4.1-4.3 of the
* PCI-PCI Bridge Spec V1.2). For non-bridges, disable
* I/O and memory access to avoid difficulty with USB
* emulation (see OHCI spec1.0a appendix B
* "Host Controller Mapping")
*/
/* determine the size of the address space */
if (baseclass != PCI_CLASS_BRIDGE) {
}
if (baseclass != PCI_CLASS_BRIDGE)
/* construct phys hi,med.lo, size hi, lo */
int hard_decode = 0;
/* i/o space */
/* XXX Adjust first 4 IDE registers */
if (pciide) {
if (subclass != PCI_MASS_IDE)
} else if (value == 0) {
/* skip base regs with size of 0 */
continue;
}
base & PCI_BASE_IO_ADDR_M : 0;
/*
* A device under a subtractive PPB can allocate
* resources from its parent bus if there is no resource
* available on its own bus.
*/
break; /* root bus already */
break;
}
}
}
/*
* first pass - gather what's there
* config - allocate regions
*/
/* take out of the resource map of the bus */
if (base != 0) {
len);
} else {
reprogram = 1;
}
if (base != 0) {
/* XXX need to worry about 64-bit? */
}
if (base == 0) {
" IO space [%d/%d/%d] BAR@0x%x"
" length 0x%x",
}
}
} else {
/* memory space */
} else {
base_hi = 0;
}
/* skip base regs with size of 0 */
if (value == 0)
continue;
if (base & PCI_BASE_PREF_M)
/*
* A device under a subtractive PPB can allocate
* resources from its parent bus if there is no resource
* available on its own bus.
*/
break; /* root bus already */
/*
* Break out as long as at least
* mem_avail is available
*/
if ((*pmem_avail &&
(phys_hi & PCI_PREFETCH_B)) ||
break;
}
}
if (config_op == CONFIG_INFO) {
/* take out of the resource map of the bus */
/* remove from PMEM and MEM space */
(void) memlist_remove(mem_avail,
(void) memlist_remove(pmem_avail,
/* only note as used in correct map */
if (phys_hi & PCI_PREFETCH_B)
else
} else {
reprogram = 1;
}
/*
* When desired, attempt a prefetchable
* allocation first
*/
if (phys_hi & PCI_PREFETCH_B) {
(void) memlist_remove(mem_avail,
}
}
/*
* If prefetchable allocation was not
* desired, or failed, attempt ordinary
* memory allocation
*/
(void) memlist_remove(
}
}
} else
"mem space [%d/%d/%d] BAR@0x%x"
" length 0x%x",
}
}
}
switch (header) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_PPB:
break;
default: /* including PCI_HEADER_CARDBUS */
goto done;
}
/*
* Add the expansion rom memory space
* Determine the size of the ROM base reg; don't write reserved bits
* ROM isn't in the PCI memory space.
*/
if (value & PCI_BASE_ROM_ENABLE)
else
value = 0;
if (value != 0) {
/* take it out of the memory resource */
}
}
/*
* Account for "legacy" (alias) video adapter resources
*/
/* add the three hard-decode, aliased address spaces for VGA */
/* VGA hard decode 0x3b0-0x3bb */
/* VGA hard decode 0x3c0-0x3df */
/* Video memory */
/* remove from MEM and PMEM space */
}
/* add the hard-decode, aliased address spaces for 8514 */
if ((baseclass == PCI_CLASS_DISPLAY) &&
(subclass == PCI_DISPLAY_VGA) &&
(progclass & PCI_DISPLAY_IF_8514)) {
/* hard decode 0x2e8 */
/* hard decode 0x2ea-0x2ef */
}
done:
"assigned-addresses",
return (reprogram);
}
static void
{
char *dev_type;
int i;
/*
* Check if it's a subtractive PPB.
*/
if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
/*
* Some BIOSes lie about max pci busses, we allow for
* such mistakes here
*/
if (subbus > pci_bios_maxbus) {
}
/* setup bus number hierarchy */
/*
* Keep track of the largest subordinate bus number (this is essential
* for peer busses because there is no other way of determining its
* subordinate bus number).
*/
/*
* Loop through subordinate busses, initializing their parent bus
* field to this bridge's parent. The subordinate busses' parent
* fields may very well be further refined later, as child bridges
* are enumerated. (The value is to note that the subordinate busses
* are not peer busses by changing their par_bus fields to anything
* other than -1.)
*/
"device_type", dev_type);
"#address-cells", 3);
"#size-cells", 2);
/*
* Collect bridge window specifications, and use them to populate
* the "avail" resources for the bus. Not all of those resources will
* end up being available; this is done top-down, and so the initial
* collection of windows populates the 'ranges' property for the
* bus node. Later, as children are found, resources are removed from
* the 'avail' list, so that it becomes the freelist for
* this point in the tree. ranges may be set again after bridge
* reprogramming in fix_ppb_res(), in which case it's set from
* used + avail.
*
* According to PPB spec, the base register should be programmed
* with a value bigger than the limit register when there are
* no resources available. This applies to io, memory, and
* prefetchable memory.
*/
/*
* io range
* We determine i/o windows that are left unconfigured by BIOS
* through its i/o enable bit as Microsoft recommends OEMs to do.
* If it is unset, we disable i/o and mark it for reconfiguration in
* later passes by setting the base > limit
*/
if (val & PCI_COMM_IO) {
} else {
io_range[0] = 0x9fff;
}
}
/* if 32-bit supported, make sure upper bits are not set */
}
}
/* mem range */
/* remove from parent resource list */
}
/* prefetchable memory range */
(uint64_t)pmem_range[0],
(uint64_t)pmem_range[0],
/* remove from parent resource list */
(uint64_t)pmem_range[0],
(uint64_t)pmem_range[0],
/* if 64-bit supported, make sure upper bits are not set */
}
}
/*
* Add VGA legacy resources to the bridge's pci_bus_res if it
* has VGA_ENABLE set. Note that we put them in 'avail',
* because that's used to populate the ranges prop; they'll be
* removed from there by the VGA device once it's found. Also,
* remove them from the parent's available list and note them as
* used in the parent.
*/
0x3b0, 0xc);
}
0x3c0, 0x20);
}
0x20000);
0xa0000, 0x20000);
}
}
}
extern const struct pci_class_strings_s class_pci[];
extern int class_pci_items;
static void
{
const char *desc;
int i;
desc = "IDE controller";
} else {
for (desc = 0, i = 0; i < class_pci_items; i++) {
break;
}
}
if (i == class_pci_items)
}
(char *)desc);
}
static void
{
return;
}
/*
* Add slot-names property for any named pci hot-plug slots
*/
static void
{
int len;
extern int pci_irq_nroutes;
char *slotcap_name;
/*
* If no irq routing table, then go with the slot-names as set up
* in pciex_slot_names_prop() from slot capability register (if any).
*/
if (pci_irq_nroutes == 0)
return;
/*
* Otherise delete the slot-names we already have and use the irq
* routing table values as returned by pci_slot_names_prop() instead,
* but keep any property of value "pcie0" as that can't be represented
* in the irq routing table.
*/
(void) ndi_prop_remove(DDI_DEV_T_NONE,
}
if (len > 0) {
/*
* Only create a peer bus node if this bus may be a peer bus.
* It may be a peer bus if the dip is NULL and if par_bus is
* -1 (par_bus is -1 if this bus was not found to be
* subordinate to any PCI-PCI bridge).
* If it's not a peer bus, then the ACPI BBN-handling code
* will remove it later.
*/
}
} else {
"IRQ routing table; Not adding slot-names "
"property for incorrect bus %d", bus);
}
}
}
/*
* Handle both PCI root and PCI-PCI bridge range properties;
* non-zero 'ppb' argument select PCI-PCI bridges versus root.
*/
static void
{
if (ppb) {
} else {
}
}
}
static void
{
/* no devinfo node - unused bus, return */
return;
/* no property is created if no ranges are present */
if (total == 0)
return;
alloc_size = total *
}
static void
{
}
}
static int
{
int i = 0;
while (list) {
/* assume 32-bit addresses */
sp->pci_phys_mid = 0;
sp->pci_size_hi = 0;
sp++, i++;
}
return (i);
}
static void
{
int i, count;
/* no devinfo node - unused bus, return */
return;
if (count == 0) /* nothing available */
return;
"available", (int *)sp,
i * sizeof (struct pci_phys_spec) / sizeof (int));
}
static void
alloc_res_array(void)
{
static int array_size = 0;
int old_size;
void *old_res;
return; /* array is big enough */
if (array_size == 0)
array_size <<= 1;
if (old_res) { /* copy content and free old array */
old_size * sizeof (struct pci_bus_resource));
}
}
static void
{
static int numioapics = 0;
/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
/* We (and the rest of the world) only support memory-mapped IOAPICs */
return;
/*
* Create a nexus node for all IOAPICs under the root node.
*/
if (ioapicsnode == NULL) {
return;
}
(void) ndi_devi_online(ioapicsnode, 0);
}
/*
* Create a child node for this IOAPIC
*/
if (ioapic_node == NULL) {
return;
}
/* Vendor and Device ID */
/* device_type */
"device_type", IOAPICS_DEV_TYPE);
/* reg */
"reg", physaddr);
}
/*
* NOTE: For PCIe slots, the name is generated from the slot number
* information obtained from Slot Capabilities register.
* For non-PCIe slots, it is generated based on the slot number
* information in the PCI IRQ table.
*/
static void
{
int len;
/* set mask to 1 as there is only one slot (i.e dev 0) */
len = 4;
slot_num);
}
/*
* Enable reporting of AER capability next pointer.
* This needs to be done only for CK8-04 devices
* by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13
* NOTE: BIOS is disabling this, it needs to be enabled temporarily
*
* This function is adapted from npe_ck804_fix_aer_ptr(), and is
* called from pci_boot.c.
*/
static void
{
NVIDIA_VENDOR_ID) &&
if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK))
}
}