Cross Reference: /illumos-gate/usr/src/uts/sun4/io/pcicfg.c

Lines Matching refs:pci_phys_hi
1514 		if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) ==
1520 			if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) ==
1984 			offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
1986 			switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
2129 			offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
2132 			switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
2162 					reg[i].pci_phys_hi ^=
2299 			switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) {
2651 			switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) {
2764 		switch (PCI_REG_ADDR_G(pci_ap[i].pci_phys_hi)) {
2940 		if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) > PCI_CONF_BASE5) &&
2941 		    (PCI_REG_REG_G(assigned[i].pci_phys_hi) != PCI_CONF_ROM))
2946 			    "%x\n", assigned[i].pci_phys_hi);
3047 	pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
3048 	pci_func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
3212 	hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
3213 	    PCI_REG_DEV_G(reg->pci_phys_hi),
3214 	    PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
3234 	addition.pci_phys_hi = hiword;
3336 	hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
3337 	    PCI_REG_DEV_G(reg->pci_phys_hi),
3338 	    PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
3367 	addition.pci_phys_hi = hiword;
4356 	p.pci_phys_hi = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
5434 			reg.pci_phys_hi = (PCI_REG_REL_M | PCI_ADDR_IO);
5444 			reg.pci_phys_hi = (PCI_REG_REL_M | PCI_ADDR_MEM32);
5773 		    reg[i].pci_phys_mid, reg[i].pci_phys_hi);
5817 	p.pci_phys_hi = PCI_ADDR_MEM32 | PCICFG_MAKE_REG_HIGH(bus, device,
6055 		phys_spec.pci_phys_hi = hiword;
6125 	phys_spec.pci_phys_hi = PCICFG_MAKE_REG_HIGH(bus, device, func, \
6128 		phys_spec.pci_phys_hi |= PCI_REG_PF_M;
6235 			if (assigned[j].pci_phys_hi == reg[i].pci_phys_hi) {
6241 				    reg[i].pci_phys_hi);
6251 					    assigned[j].pci_phys_hi,
6264 					    assigned[j].pci_phys_hi,
6276 			if (PCI_REG_BDFR_G(assigned[j].pci_phys_hi) ==
6277 			    PCI_REG_BDFR_G(reg[i].pci_phys_hi)) {
6281 				    "reg 0x%x\n", assigned[j].pci_phys_hi,
6282 				    reg[i].pci_phys_hi);
6287 				    assigned[j].pci_phys_hi) !=
6288 				    PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
6292 					    " on %s\n", reg[i].pci_phys_hi,
6321 			    reg[i].pci_phys_hi);
6375 			if (assigned[i].pci_phys_hi == phys_spec.pci_phys_hi) {
6377 				    assigned[i].pci_phys_hi);
6387 	config.pci_phys_hi = PCI_CONF_ADDR_MASK & phys_spec.pci_phys_hi;
6388 	config.pci_phys_hi &= ~PCI_REG_REG_M;
6412 	offset = PCI_REG_REG_G(phys_spec.pci_phys_hi);
6416 	if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {
6443 		switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) {
6476 			phys_spec.pci_phys_hi ^= PCI_ADDR_MEM64 ^
6540 	DEBUG1("updating assigned-addresss for %x\n",  phys_spec.pci_phys_hi);
6566 	config.pci_phys_hi = PCI_CONF_ADDR_MASK & phys_spec.pci_phys_hi;
6567 	config.pci_phys_hi &= ~PCI_REG_REG_M;
6583 	offset = PCI_REG_REG_G(phys_spec.pci_phys_hi);
6592 	if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {
6608 		switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) {
6648 	DEBUG1("updating assigned-addresss for %x\n", phys_spec.pci_phys_hi);
6694 		    oldone->pci_phys_hi);
6711 		if (assigned_copy[i].pci_phys_hi != oldone->pci_phys_hi) {