Searched refs:pci_config_get32 (Results 1 - 25 of 69) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/igb/
H A Digb_debug.c99 pci_config_get32(handle, PCI_CONF_BASE0));
102 pci_config_get32(handle, PCI_CONF_BASE1));
105 pci_config_get32(handle, PCI_CONF_BASE2));
108 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3);
114 pci_config_get32(handle, PCI_CONF_BASE4));
117 pci_config_get32(handle, PCI_CONF_BASE5));
120 pci_config_get32(handle, PCI_CONF_CIS));
129 pci_config_get32(handle, PCI_CONF_ROM));
188 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));
191 pci_config_get32(handl
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/illumos-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c224 pci_config_get32(handle, PCI_CONF_BASE0));
227 pci_config_get32(handle, PCI_CONF_BASE1));
230 pci_config_get32(handle, PCI_CONF_BASE2));
233 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3);
239 pci_config_get32(handle, PCI_CONF_BASE4));
242 pci_config_get32(handle, PCI_CONF_BASE5));
245 pci_config_get32(handle, PCI_CONF_CIS));
254 pci_config_get32(handle, PCI_CONF_ROM));
313 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));
316 pci_config_get32(handl
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/illumos-gate/usr/src/uts/intel/io/dktp/controller/ata/
H A Dsil3xxx.h89 rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \
/illumos-gate/usr/src/uts/intel/io/agpgart/
H A Damd64_gart.c42 value = pci_config_get32(sc->gsoft_pcihdl,
54 value = pci_config_get32(sc->gsoft_pcihdl, AMD64_APERTURE_CONTROL);
93 value = pci_config_get32(sc->gsoft_pcihdl, AMD64_GART_CACHE_CTL);
107 aper_ctl = pci_config_get32(sc->gsoft_pcihdl, AMD64_APERTURE_CONTROL);
109 aper_base = pci_config_get32(sc->gsoft_pcihdl, AMD64_APERTURE_BASE);
110 gart_ctl = pci_config_get32(sc->gsoft_pcihdl, AMD64_GART_CACHE_CTL);
111 gart_base = pci_config_get32(sc->gsoft_pcihdl, AMD64_GART_BASE);
H A Dagptarget.c143 ncapid = pci_config_get32(pci_handle, nextcap);
182 aper_base = pci_config_get32(softstate->tsoft_pcihdl,
556 softstate->tsoft_devid = pci_config_get32(softstate->tsoft_pcihdl,
693 value = pci_config_get32(st->tsoft_pcihdl, cap);
697 info.iagp_mode = pci_config_get32(st->tsoft_pcihdl,
808 value1 = pci_config_get32(st->tsoft_pcihdl,
/illumos-gate/usr/src/uts/common/io/
H A Dpci_cap.c94 if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
106 if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
181 if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
276 data = pci_config_get32(h, offset);
342 if ((*ptr++ = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)
/illumos-gate/usr/src/uts/common/io/scsi/adapters/pmcs/
H A Dpmcs_fwlog.c746 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_REVID));
749 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_CACHE_LINESZ));
751 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE0));
753 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE1));
755 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE2));
757 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE3));
759 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE4));
761 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE5));
763 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_SUBVENID));
765 pci_config_get32(pw
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/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Ddb21554.c1034 pci_config_get32(dbp->conf_handle,
1039 pci_config_get32(dbp->conf_handle,
1044 pci_config_get32(dbp->conf_handle,
1051 ((pci_config_get32(dbp->conf_handle,
1055 ((pci_config_get32(dbp->conf_handle,
1059 ((pci_config_get32(dbp->conf_handle,
1063 ((pci_config_get32(dbp->conf_handle,
1067 ((pci_config_get32(dbp->conf_handle,
1208 dvma_size[0] = pci_config_get32(dbp->conf_handle,
1216 dvma_size[0] = pci_config_get32(db
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/illumos-gate/usr/src/uts/common/io/e1000g/
H A De1000g_debug.c427 pci_config_get32(handle, PCI_CONF_CIS));
436 pci_config_get32(handle, PCI_CONF_ROM));
495 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));
498 pci_config_get32(handle, offset + 0x8));
519 pci_config_get32(handle, offset + PCIE_DEVCAP));
528 pci_config_get32(handle, offset + PCIE_LINKCAP));
542 uint32_t base = pci_config_get32(handle, offset);
584 size = pci_config_get32(handle, offset);
/illumos-gate/usr/src/uts/common/io/cardbus/
H A Dcardbus_hp.c1695 { "BASE0 =", 0x10, (int(*)())pci_config_get32, "%s 0x%08x" },
1696 { "BASE1 =", 0x14, (int(*)())pci_config_get32, "%s 0x%08x" },
1697 { "BASE2 =", 0x18, (int(*)())pci_config_get32, "%s 0x%08x" },
1698 { "BASE3 =", 0x1c, (int(*)())pci_config_get32, "%s 0x%08x" },
1699 { "BASE4 =", 0x20, (int(*)())pci_config_get32, "%s 0x%08x" },
1700 { "CIS Pointer =", 0x28, (int(*)())pci_config_get32, "%s 0x%08x" },
1713 { "MemBase Addr=", 0x10, (int(*)())pci_config_get32, "%s 0x%08x" },
1718 { "Mem0 Base =", 0x1c, (int(*)())pci_config_get32, "%s 0x%08x" },
1719 { "Mem0 Limit =", 0x20, (int(*)())pci_config_get32, "%s 0x%08x" },
1720 { "Mem1 Base =", 0x24, (int(*)())pci_config_get32, "
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H A Dcardbus_cfg.c905 pci_config_get32(handle, offset), offset);
908 pci_config_get32(handle, offset+4),
920 request = pci_config_get32(handle, offset);
933 pci_config_get32(handle, offset),
940 pci_config_get32(handle, offset+4),
946 pci_config_get32(handle, offset),
959 pci_config_get32(handle, offset), offset);
1145 pci_config_get32(phdl->handle, phdl->io_decode_reg));
2724 request = pci_config_get32(config_handle,
2807 pci_config_get32(config_handl
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/illumos-gate/usr/src/uts/intel/io/mc-amd/
H A Dmcamd_pcicfg.c84 return (pci_config_get32(hdlp->cfh_hdl, offset));
/illumos-gate/usr/src/uts/common/os/
H A Dsunpci.c83 pci_config_get32(ddi_acc_handle_t handle, off_t offset) function
467 *p = pci_config_get32(confhdl, offset);
519 chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);
520 chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
521 chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);
522 chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);
523 chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4);
524 chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);
654 *regbuf = pci_config_get32(confhdl, cap_ptr);
900 (void) pci_config_get32(confhd
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H A Dpcifm.c114 pcix_ecc_regs->pcix_ecc_ctlstat = pci_config_get32(erpt_p->pe_hdl,
121 pcix_ecc_regs->pcix_ecc_fstaddr = pci_config_get32(erpt_p->pe_hdl,
124 pcix_ecc_regs->pcix_ecc_secaddr = pci_config_get32(erpt_p->pe_hdl,
127 pcix_ecc_regs->pcix_ecc_attr = pci_config_get32((
149 pcix_bdg_regs->pcix_bdg_stat = pci_config_get32(erpt_p->pe_hdl,
177 pcix_regs->pcix_status = pci_config_get32(erpt_p->pe_hdl,
/illumos-gate/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c66 *val = pci_config_get32(sc->pci_regh, reg);
/illumos-gate/usr/src/uts/intel/io/agpmaster/
H A Dagpmaster.c342 value = pci_config_get32(pci_acc_hdl, gmadr_off);
372 pci_config_get32(pci_acc_hdl, PCI_CONF_VENID);
470 value = pci_config_get32(softc->agpm_acc_hdl, cap);
474 info.agpi_mode = pci_config_get32(
579 ncapid = pci_config_get32(acc_handle, nextcap);
/illumos-gate/usr/src/uts/common/io/chxge/
H A Dglue.c118 *val = pci_config_get32(obj->ch_hpci, reg);
264 pe->pe_reg_val = reg = pci_config_get32(chp->ch_hpci, pe->addr);
278 reg = pci_config_get32(chp->ch_hpci, pe->addr);
/illumos-gate/usr/src/uts/intel/io/pciex/
H A Dpcieb_x86.c497 data = (uint32_t)pci_config_get32(cfg_hdl,
503 value = (uint32_t)pci_config_get32(cfg_hdl,
592 pexctrl = pci_config_get32(bus_p->bus_cfg_hdl,
/illumos-gate/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c419 pci_config_get32(config_handle, PCI_CONF_BASE0));
421 pci_config_get32(config_handle, PCI_CONF_BASE1));
433 pci_config_get32(config_handle, PCI_CONF_BASE2));
435 pci_config_get32(config_handle, PCI_CONF_BASE3));
437 pci_config_get32(config_handle, PCI_CONF_BASE4));
439 pci_config_get32(config_handle, PCI_CONF_BASE5));
441 pci_config_get32(config_handle, PCI_CONF_CIS));
447 pci_config_get32(config_handle, PCI_CONF_ROM));
490 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH));
492 pci_config_get32(config_handl
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/illumos-gate/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_attach.c585 global_swap = pci_config_get32(soft_state->pci_config,
595 global_swap = pci_config_get32(soft_state->pci_config,
676 global_swap = pci_config_get32(soft_state->pci_config,
/illumos-gate/usr/src/uts/sun4u/io/
H A Dpmubus.c459 value = pci_config_get32(softsp->pmubus_reghdl, offset) & mask;
557 tmp = pci_config_get32(softsp->pmubus_reghdl, offset);
573 tmp = pci_config_get32(softsp->pmubus_reghdl, offset);
/illumos-gate/usr/src/uts/sun4/io/
H A Dpcicfg.c448 pci_config_get32(config_handle, PCI_CONF_BASE0));
450 pci_config_get32(config_handle, PCI_CONF_BASE1));
462 pci_config_get32(config_handle, PCI_CONF_BASE2));
464 pci_config_get32(config_handle, PCI_CONF_BASE3));
466 pci_config_get32(config_handle, PCI_CONF_BASE4));
468 pci_config_get32(config_handle, PCI_CONF_BASE5));
470 pci_config_get32(config_handle, PCI_CONF_CIS));
476 pci_config_get32(config_handle, PCI_CONF_ROM));
520 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH));
522 pci_config_get32(config_handl
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/illumos-gate/usr/src/uts/intel/io/amr/
H A Damrreg.h640 #define AMR_QGET_IDB(sc) pci_config_get32(sc->regsmap_handle, \
644 #define AMR_QGET_ODB(sc) pci_config_get32(sc->regsmap_handle, \
/illumos-gate/usr/src/uts/common/io/ntxn/
H A Dunm_gem.c362 pexsizes = pci_config_get32(pci_cfg_hdl, 0xd8);
1109 control = pci_config_get32(pcihdl, 0xD0);
1114 control = pci_config_get32(pcihdl, 0xC8);
1115 control = pci_config_get32(pcihdl, 0xC8);
/illumos-gate/usr/src/uts/common/io/xge/drv/
H A Dxge_osdep.h311 (*(val) = pci_config_get32(cfgh, where))

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