080575042aba2197b425ebfd52061dea061a9aa1xy * This file is provided under a CDDLv1 license. When using or
080575042aba2197b425ebfd52061dea061a9aa1xy * redistributing this file, you may do so under this license.
080575042aba2197b425ebfd52061dea061a9aa1xy * In redistributing this file this license must be included
080575042aba2197b425ebfd52061dea061a9aa1xy * and no other modification of this header file is permitted.
080575042aba2197b425ebfd52061dea061a9aa1xy * CDDL LICENSE SUMMARY
caf05df5c10c960028f122b1b02a3f7d8f892c31Miles Xu, Sun Microsystems * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
080575042aba2197b425ebfd52061dea061a9aa1xy * The contents of this file are subject to the terms of Version
080575042aba2197b425ebfd52061dea061a9aa1xy * 1.0 of the Common Development and Distribution License (the "License").
080575042aba2197b425ebfd52061dea061a9aa1xy * You should have received a copy of the License with this software.
080575042aba2197b425ebfd52061dea061a9aa1xy * You can obtain a copy of the License at
080575042aba2197b425ebfd52061dea061a9aa1xy * See the License for the specific language governing permissions
080575042aba2197b425ebfd52061dea061a9aa1xy * and limitations under the License.
caf05df5c10c960028f122b1b02a3f7d8f892c31Miles Xu, Sun Microsystems * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
080575042aba2197b425ebfd52061dea061a9aa1xy * Use is subject to license terms of the CDDLv1.
080575042aba2197b425ebfd52061dea061a9aa1xy * **********************************************************************
080575042aba2197b425ebfd52061dea061a9aa1xy * Module Name: *
080575042aba2197b425ebfd52061dea061a9aa1xy * Abstract: *
25f2d433de915875c8393f0b0dc14aa155997ad0xy * This module includes the debug routines *
080575042aba2197b425ebfd52061dea061a9aa1xy * **********************************************************************
592a4d85662412bade15f3d9e9e0cbcf8514348ccc#define NUM_REGS 155 /* must match the array initializer */
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyytypedef struct {
caf05df5c10c960028f122b1b02a3f7d8f892c31Miles Xu, Sun Microsystems#endif /* E1000G_DEBUG */
25f2d433de915875c8393f0b0dc14aa155997ad0xy switch (level) {
080575042aba2197b425ebfd52061dea061a9aa1xy ddi_get_name(Adapter->dip), ddi_get_instance(Adapter->dip));
080575042aba2197b425ebfd52061dea061a9aa1xy * va_start uses built in macro __builtin_va_alist from the
080575042aba2197b425ebfd52061dea061a9aa1xy * compiler libs which requires compiler system to have
080575042aba2197b425ebfd52061dea061a9aa1xy * __BUILTIN_VA_ARG_INCR defined.
080575042aba2197b425ebfd52061dea061a9aa1xy * Many compilation systems depend upon the use of special functions
080575042aba2197b425ebfd52061dea061a9aa1xy * built into the the compilation system to handle variable argument
080575042aba2197b425ebfd52061dea061a9aa1xy * lists and stack allocations. The method to obtain this in SunOS
080575042aba2197b425ebfd52061dea061a9aa1xy * is to define the feature test macro "__BUILTIN_VA_ARG_INCR" which
080575042aba2197b425ebfd52061dea061a9aa1xy * enables the following special built-in functions:
080575042aba2197b425ebfd52061dea061a9aa1xy * __builtin_alloca
080575042aba2197b425ebfd52061dea061a9aa1xy * __builtin_va_alist
080575042aba2197b425ebfd52061dea061a9aa1xy * __builtin_va_arg_incr
080575042aba2197b425ebfd52061dea061a9aa1xy * It is intended that the compilation system define this feature test
080575042aba2197b425ebfd52061dea061a9aa1xy * macro, not the user of the system.
080575042aba2197b425ebfd52061dea061a9aa1xy * The tests on the processor type are to provide a transitional period
080575042aba2197b425ebfd52061dea061a9aa1xy * for existing compilation systems, and may be removed in a future
080575042aba2197b425ebfd52061dea061a9aa1xy * release.
080575042aba2197b425ebfd52061dea061a9aa1xy * Using GNU gcc compiler it doesn't expand to va_start....
25f2d433de915875c8393f0b0dc14aa155997ad0xy if ((e1000g_log_mode & E1000G_LOG_ALL) == E1000G_LOG_ALL)
25f2d433de915875c8393f0b0dc14aa155997ad0xy else /* if they are not set properly then do both */
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy {128, 256, 512, 1024, 2048, 4096, 16 * 1024, 32 * 1024, 64 * 1024};
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "eeprom_dump size field: %d eeprom bytes: %d\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "e1000_read_nvm hebs: %d\n", ((size_field & 0x000f) >> 10));
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "dump eeprom %d lines of %d words per line\n", lines, WPL);
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy for (i = 0; i < lines; i++) {
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "0x%04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy * phy_dump - dump important phy registers
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy /* offset to each phy register */
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy 30, 31, 0x1796, 0x187A, 0x1895, 0x1F30, 0x1F35, 0x1F3E, 0x1F54,
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy 0x1F55, 0x1F56, 0x1F72, 0x1F76, 0x1F77, 0x1F78, 0x1F79, 0x1F98,
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy 0x2010, 0x2011, 0x20DC, 0x20DD, 0x20DE, 0x28B4, 0x2F52, 0x2F5B,
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy for (i = 0; i < ((sizeof (offset)) / sizeof (offset[0])); i++) {
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy if (stat == 0) {
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "phyreg offset: %d value: 0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "phyreg offset: %d ERROR: 0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy return (ddi_get32(((struct e1000g_osdep *)(hw)->back)->reg_handle,
fe62dec3a38f1f79ffe68417df75dbbb58135bb7Chen-Liang Xu (uint32_t *)((uintptr_t)(hw)->hw_addr + offset)));
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy * mac_dump - dump important mac registers
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy /* {name, offset} for each mac register */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc {"RDBAH(0)", E1000_RDBAH(0)}, {"RDLEN(0)", E1000_RDLEN(0)},
592a4d85662412bade15f3d9e9e0cbcf8514348ccc {"RDBAH(1)", E1000_RDBAH(1)}, {"RDLEN(1)", E1000_RDLEN(1)},
592a4d85662412bade15f3d9e9e0cbcf8514348ccc {"TDBAH(0)", E1000_TDBAH(0)}, {"TDLEN(0)", E1000_TDLEN(0)},
592a4d85662412bade15f3d9e9e0cbcf8514348ccc {"TDBAL(1)", E1000_TDBAL(1)}, {"TDBAH(1)", E1000_TDBAH(1)},
592a4d85662412bade15f3d9e9e0cbcf8514348ccc {"TDT(1)", E1000_TDT(1)}, {"TXDCTL(1)", E1000_TXDCTL(1)},
592a4d85662412bade15f3d9e9e0cbcf8514348ccc {"TARC(1)", E1000_TARC(1)}, {"ALGNERRC", E1000_ALGNERRC},
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy {"ICTXQEC", E1000_ICTXQEC}, {"ICTXQMTC", E1000_ICTXQMTC},
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy for (i = 0; i < NUM_REGS; i++) {
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "macreg %10s offset: 0x%x value: 0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy e1000g_log(Adapter, CE_CONT, "Begin dump PCI config space\n");
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_VENID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_DEVID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_COMMAND:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_STATUS:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_REVID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_PROG_CLASS:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_SUB_CLASS:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_BAS_CLASS:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_CACHE_LINESZ:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_LATENCY_TIMER:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_HEADER_TYPE:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_BIST:\t0x%x\n",
592a4d85662412bade15f3d9e9e0cbcf8514348ccc pciconfig_bar(Adapter, PCI_CONF_BASE0, "PCI_CONF_BASE0");
592a4d85662412bade15f3d9e9e0cbcf8514348ccc pciconfig_bar(Adapter, PCI_CONF_BASE1, "PCI_CONF_BASE1");
592a4d85662412bade15f3d9e9e0cbcf8514348ccc pciconfig_bar(Adapter, PCI_CONF_BASE2, "PCI_CONF_BASE2");
592a4d85662412bade15f3d9e9e0cbcf8514348ccc pciconfig_bar(Adapter, PCI_CONF_BASE3, "PCI_CONF_BASE3");
592a4d85662412bade15f3d9e9e0cbcf8514348ccc pciconfig_bar(Adapter, PCI_CONF_BASE4, "PCI_CONF_BASE4");
592a4d85662412bade15f3d9e9e0cbcf8514348ccc pciconfig_bar(Adapter, PCI_CONF_BASE5, "PCI_CONF_BASE5");
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_CIS:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_SUBVENID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_SUBSYSID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_ROM:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_ILINE:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_IPIN:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_MIN_G:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_CONF_MAX_L:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy /* Power Management */
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_PM_CAP_ID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_PM_CAP:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_PM_CSR:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_PM_CSR_BSE:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_PM_DATA:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy /* MSI Configuration */
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_MSI_CAP_ID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_MSI_CTRL:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_MSI_ADDR:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_MSI_ADDR_HI:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCI_MSI_DATA:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy /* PCI Express Configuration */
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_CAP_ID:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy next_ptr = pci_config_get8(handle, offset + PCIE_CAP_NEXT_PTR);
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_PCIECAP:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_DEVCAP:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_DEVCTL:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_DEVSTS:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_LINKCAP:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_LINKCTL:\t0x%x\n",
4914a7d0d1ee59f8cc21b19bfd7979cb65681eacyy "PCIE_LINKSTS:\t0x%x\n",
592a4d85662412bade15f3d9e9e0cbcf8514348cccpciconfig_bar(void *instance, uint32_t offset, char *name)
592a4d85662412bade15f3d9e9e0cbcf8514348ccc char tag_mem[32]; /* tag to show memory characteristiccs */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* base address zero, simple print */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc if (base == 0) {
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* base address non-zero, get size */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* i/o factors that decode from the base address */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* memory factors that decode from the base address */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* disable memory decode */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc pci_config_put16(handle, PCI_CONF_COMM, (comm & ~bits_comm));
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* write to base register */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* read back & compute size */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* restore base register */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* re-enable memory decode */
592a4d85662412bade15f3d9e9e0cbcf8514348ccc /* print results */
caf05df5c10c960028f122b1b02a3f7d8f892c31Miles Xu, Sun Microsystems#endif /* E1000G_DEBUG */