507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/*
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * CDDL HEADER START
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf *
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * The contents of this file are subject to the terms of the
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Common Development and Distribution License (the "License").
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * You may not use this file except in compliance with the License.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf *
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * or http://www.opensolaris.org/os/licensing.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * See the License for the specific language governing permissions
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * and limitations under the License.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf *
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * When distributing Covered Code, include this CDDL HEADER in each
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * If applicable, add the following below this CDDL HEADER, with the
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * fields enclosed by brackets "[]" replaced with your own identifying
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * information: Portions Copyright [yyyy] [name of copyright owner]
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf *
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * CDDL HEADER END
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/*
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Use is subject to license terms.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#ifndef _SIL3XXX_H
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define _SIL3XXX_H
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#pragma ident "%Z%%M% %I% %E% SMI"
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#ifdef __cplusplus
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfextern "C" {
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#endif
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/*
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * PCI IDs
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SILICON_IMAGE_VENDOR_ID 0x1095
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SIL3112_DEVICE_ID 0x3112
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SIL3114_DEVICE_ID 0x3114
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SIL3512_DEVICE_ID 0x3512
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Base Register 5 Indirect Address Offset */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define PCI_CONF_BA5_IND_ADDRESS 0xc0
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define PCI_CONF_BA5_IND_ACCESS 0xc4
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/*
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * FIS Configuration channel offsets
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Sil3114 has 4 channels
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Sil3112 has 2 channels
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Sil3512 has 2 channels
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SFISCFG_0 0x14c /* SFISCfg Channel 0 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SFISCFG_1 0x1cc /* SFISCfg Channel 1 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SFISCFG_2 0x34c /* SFISCfg Channel 2 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SFISCFG_3 0x3cc /* SFISCfg Channel 3 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/*
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * FIFO count and contrl offsets for channel 0-4
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define FIFO_CNTCTL_0 0x40
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define FIFO_CNTCTL_1 0x44
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define FIFO_CNTCTL_2 0x240
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define FIFO_CNTCTL_3 0x244
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/*
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Errata Sil-AN-0028-C (Sil3512 Rev 0.3)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Errata Sil-AN-0109-B2 (Sil3114 Rev 0.3)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * To prevent erroneous ERR set for queued DMA transfers
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * greater then 8k, FIS reception for FIS0cfg needs to be set
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * to Accept FIS without Interlock
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Default SFISCfg value of 0x10401555 in channel SFISCfg
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * register need to be changed to 0x10401554.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define SFISCFG_ERRATA 0x10401554
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define PUT_BAR5_INDIRECT(handle, address, value) \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf{\
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf pci_config_put32(handle, PCI_CONF_BA5_IND_ACCESS, value); \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf}
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define GET_BAR5_INDIRECT(handle, address, rval) \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf{\
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf}
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfuint_t sil3xxx_init_controller(dev_info_t *, ushort_t, ushort_t);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#ifdef __cplusplus
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf}
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#endif
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#endif /* _SIL3XXX_H */