cxgbe/t4nex/adapter.c

56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana/*
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * This file and its contents are supplied under the terms of the
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * Common Development and Distribution License ("CDDL"), version 1.0.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * You may only use this file in accordance with the terms of version
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * 1.0 of the CDDL.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana *
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * A full copy of the text of the CDDL should have accompanied this
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * source. A copy of the CDDL is also available via the Internet at
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * http://www.illumos.org/license/CDDL.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana/*
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * This file is part of the Chelsio T4 support code.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana *
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * Copyright (C) 2011-2013 Chelsio Communications.  All rights reserved.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana *
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * release for licensing terms and conditions.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#include "common.h"
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanauint32_t
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_read_reg(struct adapter *sc, uint32_t reg)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    /* LINTED: E_BAD_PTR_CAST_ALIGN */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg)));
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    /* LINTED: E_BAD_PTR_CAST_ALIGN */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    *val = pci_config_get8(sc->pci_regh, reg);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    pci_config_put8(sc->pci_regh, reg, val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    *val = pci_config_get16(sc->pci_regh, reg);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    pci_config_put16(sc->pci_regh, reg, val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    *val = pci_config_get32(sc->pci_regh, reg);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    pci_config_put32(sc->pci_regh, reg, val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanauint64_t
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_read_reg64(struct adapter *sc, uint32_t reg)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    /* LINTED: E_BAD_PTR_CAST_ALIGN */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg)));
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    /* LINTED: E_BAD_PTR_CAST_ALIGN */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanastruct port_info *
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaadap2pinfo(struct adapter *sc, int idx)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    return (sc->port[idx]);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanabool
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanais_10G_port(const struct port_info *pi)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanastruct sge_rxq *
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaiq_to_rxq(struct sge_iq *iq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    return (container_of(iq, struct sge_rxq, iq));
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanat4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana{
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    int rc;
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    TXQ_LOCK(wrq);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    rc = t4_wrq_tx_locked(sc, wrq, m);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    TXQ_UNLOCK(wrq);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana    return (rc);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana}