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Searched refs:csr_base (Results 1 - 6 of 6) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/io/px/
H A D	px_hlib.c	291 hvio_ib_init(caddr_t csr_base, pxu_t pxu_p) argument 297 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE)); 300 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE)); 303 CSR_XR(csr_base, IMU_INTERRUPT_STATUS)); 306 CSR_XR(csr_base, IMU_ERROR_STATUS_CLEAR)); 314 ilu_init(caddr_t csr_base, pxu_t pxu_p) argument 320 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE)); 323 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE)); 326 CSR_XR(csr_base, ILU_INTERRUPT_STATUS)); 329 CSR_XR(csr_base, ILU_ERROR_STATUS_CLEA 337 tlu_init(caddr_t csr_base, pxu_t pxu_p) argument 728 lpu_init(caddr_t csr_base, pxu_t pxu_p) argument 1516 dlu_init(caddr_t csr_base, pxu_t pxu_p) argument 1547 dmc_init(caddr_t csr_base, pxu_t pxu_p) argument 1586 hvio_pec_init(caddr_t csr_base, pxu_t pxu_p) argument 1680 mmu_tsb_entries(caddr_t csr_base, pxu_t pxu_p) argument 1698 hvio_mmu_init(caddr_t csr_base, pxu_t pxu_p) argument 2988 px_send_pme_turnoff(caddr_t csr_base) argument 3014 px_link_wait4l1idle(caddr_t csr_base) argument 3033 px_link_retrain(caddr_t csr_base) argument 3058 px_enable_detect_quiet(caddr_t csr_base) argument 3068 oberon_hp_pwron(caddr_t csr_base) argument 3265 oberon_hp_pwroff(caddr_t csr_base) argument 3371 caddr_t csr_base = (caddr_t )cookie; local 3407 caddr_t csr_base = (caddr_t *)cookie; local [all...]
H A D	px_err_impl.h	97 (dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, \ 105 (dev_info_t rpdip, caddr_t csr_base, uint64_t ss_reg, \ 119 int px_err_hw_reset_handle(dev_info_t rpdip, caddr_t csr_base, 122 int px_err_panic_handle(dev_info_t rpdip, caddr_t csr_base, 125 int px_err_protected_handle(dev_info_t rpdip, caddr_t csr_base, 128 int px_err_no_panic_handle(dev_info_t rpdip, caddr_t csr_base, 131 int px_err_no_error_handle(dev_info_t rpdip, caddr_t csr_base, 156 int px_err_jbc_merge_handle(dev_info_t rpdip, caddr_t csr_base, 159 int px_err_jbc_jbusint_in_handle(dev_info_t rpdip, caddr_t csr_base, 162 int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, [all...]
H A D	px_err.c	725 * Proper csr_base is responsibility of the caller. (Called from px_lib_dev_init 733 px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base) argument 741 CSR_XS(csr_base, reg_desc_p->log_addr, log_mask); 752 CSR_XS(csr_base, reg_desc_p->enable_addr, 0); 753 CSR_XS(csr_base, reg_desc_p->clear_addr, -1); 754 CSR_XS(csr_base, reg_desc_p->enable_addr, intr_mask); 756 CSR_XR(csr_base, reg_desc_p->enable_addr)); 758 CSR_XR(csr_base, reg_desc_p->status_addr)); 760 CSR_XR(csr_base, reg_desc_p->clear_addr)); 763 CSR_XR(csr_base, reg_desc_ 768 px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base) argument 782 px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base, boolean_t enable) argument 868 caddr_t csr_base; local 910 caddr_t csr_base; local 1074 px_err_hw_reset_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1088 px_err_panic_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1101 px_err_protected_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1115 px_err_no_panic_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1129 px_err_no_error_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1358 px_err_jbc_merge_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1413 px_err_jbc_jbusint_in_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1493 px_err_jbc_dmcint_odcd_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1516 px_jbc_pcitool_addr_match(dev_info_t rpdip, caddr_t csr_base) argument 1538 px_err_jbc_safe_acc_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1644 px_err_imu_eq_ovfl_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1786 px_err_mmu_rbne_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1817 px_err_mmu_tfa_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1846 px_err_mmu_parity_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1876 px_err_wuc_ruc_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1914 px_err_tlu_lup_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1936 px_err_tlu_ldn_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 1971 px_err_pciex_ue_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t err_bit_descr) argument 2126 px_err_pciex_ce_handle(dev_info_t rpdip, caddr_t csr_base, ddi_fm_error_t derr, px_err_reg_desc_t err_reg_descr, px_err_bit_desc_t *err_bit_descr) argument [all...]
H A D	px_err.h	`55 void px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base); 56 void px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base); 57 void px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base,`
H A D	px_lib4u.h	`301 extern void hvio_ib_init(caddr_t csr_base, pxu_t pxu_p); 302 extern void hvio_mmu_init(caddr_t csr_base, pxu_t pxu_p); 303 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 394 extern int px_send_pme_turnoff(caddr_t csr_base); 395 extern int px_link_wait4l1idle(caddr_t csr_base); 396 extern int px_link_retrain(caddr_t csr_base); 397 extern void px_enable_detect_quiet(caddr_t csr_base);`
H A D	px_lib4u.c	182 caddr_t xbc_csr_base, csr_base; local 218 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 242 hvio_ib_init(csr_base, pxu_p); 243 hvio_pec_init(csr_base, pxu_p); 244 hvio_mmu_init(csr_base, pxu_p); 259 if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3)) 266 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 270 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 280 *dev_hdl = (devhandle_t)csr_base; 293 caddr_t csr_base; local 1874 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; local 2021 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; local 2381 caddr_t csr_base; local 2630 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; local 2646 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; local 2659 caddr_t csr_base; local 2680 caddr_t csr_base; local [all...]

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