Lines Matching refs:csr_base
725 * Proper csr_base is responsibility of the caller. (Called from px_lib_dev_init
733 px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base)
741 CSR_XS(csr_base, reg_desc_p->log_addr, log_mask);
752 CSR_XS(csr_base, reg_desc_p->enable_addr, 0);
753 CSR_XS(csr_base, reg_desc_p->clear_addr, -1);
754 CSR_XS(csr_base, reg_desc_p->enable_addr, intr_mask);
756 CSR_XR(csr_base, reg_desc_p->enable_addr));
758 CSR_XR(csr_base, reg_desc_p->status_addr));
760 CSR_XR(csr_base, reg_desc_p->clear_addr));
763 CSR_XR(csr_base, reg_desc_p->log_addr));
768 px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base)
774 CSR_XS(csr_base, reg_desc_p->log_addr, val);
775 CSR_XS(csr_base, reg_desc_p->enable_addr, val);
782 px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base, boolean_t enable)
797 px_err_reg_func(reg_id, csr_base);
868 caddr_t csr_base;
879 csr_base = xbc_csr_base;
882 csr_base = pec_csr_base;
888 ss_p->err_status[reg_id] = CSR_XR(csr_base,
910 caddr_t csr_base;
937 csr_base = (caddr_t)pxu_p->px_address[err_reg_tbl->reg_bank];
969 biterr = err_handler(rpdip, csr_base, derr,
984 (void) erpt_handler(rpdip, csr_base, ss_reg,
990 CSR_XS(csr_base, clear_addr, ss_reg);
1074 px_err_hw_reset_handle(dev_info_t *rpdip, caddr_t csr_base,
1088 px_err_panic_handle(dev_info_t *rpdip, caddr_t csr_base,
1101 px_err_protected_handle(dev_info_t *rpdip, caddr_t csr_base,
1115 px_err_no_panic_handle(dev_info_t *rpdip, caddr_t csr_base,
1129 px_err_no_error_handle(dev_info_t *rpdip, caddr_t csr_base,
1186 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG);
1246 ubc_intr_status = CSR_XR(csr_base, UBC_INTERRUPT_STATUS);
1265 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE),
1267 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE),
1270 CSR_XR(csr_base, UBC_ERROR_STATUS_SET),
1283 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE),
1285 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE),
1288 CSR_XR(csr_base, UBC_ERROR_STATUS_SET),
1310 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE),
1312 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE),
1316 CSR_XR(csr_base, JBC_ERROR_STATUS_SET),
1318 CSR_XR(csr_base, FATAL_ERROR_LOG_1),
1320 CSR_XR(csr_base, FATAL_ERROR_LOG_2),
1337 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE),
1339 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE),
1343 CSR_XR(csr_base, JBC_ERROR_STATUS_SET),
1345 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG),
1358 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base,
1366 * paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG);
1375 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr,
1390 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE),
1392 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE),
1396 CSR_XR(csr_base, JBC_ERROR_STATUS_SET),
1398 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG),
1400 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2),
1413 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base,
1421 * paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG);
1430 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr,
1446 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE),
1448 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE),
1452 CSR_XR(csr_base, JBC_ERROR_STATUS_SET),
1454 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG),
1456 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2),
1473 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE),
1475 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE),
1479 CSR_XR(csr_base, JBC_ERROR_STATUS_SET),
1481 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG),
1493 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base,
1501 * paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG);
1510 return (px_err_panic_handle(rpdip, csr_base, derr, err_reg_descr,
1516 px_jbc_pcitool_addr_match(dev_info_t *rpdip, caddr_t csr_base)
1522 (caddr_t)CSR_FR(csr_base, DMCINT_ODCD_ERROR_LOG, ADDRESS);
1538 px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base,
1545 return (px_err_panic_handle(rpdip, csr_base, derr,
1558 (px_jbc_pcitool_addr_match(rpdip, csr_base)))
1559 return (px_err_protected_handle(rpdip, csr_base, derr,
1562 return (px_err_jbc_dmcint_odcd_handle(rpdip, csr_base, derr,
1577 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE),
1579 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE),
1583 CSR_XR(csr_base, JBC_ERROR_STATUS_SET),
1585 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG),
1602 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE),
1604 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE),
1608 CSR_XR(csr_base, JBC_ERROR_STATUS_SET),
1610 CSR_XR(csr_base, CSR_ERROR_LOG),
1627 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE),
1629 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE),
1633 CSR_XR(csr_base, IMU_ERROR_STATUS_SET),
1635 CSR_XR(csr_base, IMU_RDS_ERROR_LOG),
1644 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base,
1653 return (px_err_panic_handle(rpdip, csr_base, derr,
1656 return (px_err_no_panic_handle(rpdip, csr_base, derr,
1672 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE),
1674 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE),
1678 CSR_XR(csr_base, IMU_ERROR_STATUS_SET),
1680 CSR_XR(csr_base, IMU_SCS_ERROR_LOG),
1697 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE),
1699 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE),
1703 CSR_XR(csr_base, IMU_ERROR_STATUS_SET),
1719 fault_bdf = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS)
1734 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE),
1736 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE),
1740 CSR_XR(csr_base, MMU_ERROR_STATUS_SET),
1742 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS),
1744 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS),
1761 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE),
1763 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE),
1767 CSR_XR(csr_base, MMU_ERROR_STATUS_SET),
1786 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base,
1795 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID);
1800 return (px_err_no_panic_handle(rpdip, csr_base, derr, err_reg_descr,
1817 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base,
1826 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID);
1831 return (px_err_no_panic_handle(rpdip, csr_base, derr, err_reg_descr,
1846 px_err_mmu_parity_handle(dev_info_t *rpdip, caddr_t csr_base,
1857 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS);
1858 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID);
1864 return (px_err_panic_handle(rpdip, csr_base, derr,
1867 return (px_err_no_panic_handle(rpdip, csr_base, derr,
1876 px_err_wuc_ruc_handle(dev_info_t *rpdip, caddr_t csr_base,
1889 data = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG);
1892 data = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG);
1901 return (px_err_protected_handle(rpdip, csr_base, derr,
1904 return (px_err_no_panic_handle(rpdip, csr_base, derr,
1914 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base,
1936 px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base,
1956 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE),
1958 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE),
1962 CSR_XR(csr_base, ILU_ERROR_STATUS_SET),
1971 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base,
1990 log = CSR_XR(csr_base,
1995 log = CSR_XR(csr_base,
2007 return (px_err_panic_handle(rpdip, csr_base, derr,
2010 return (px_err_no_panic_handle(rpdip, csr_base, derr,
2026 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE),
2028 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE),
2032 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET),
2034 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG),
2036 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG),
2053 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE),
2055 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE),
2059 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET),
2061 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG),
2063 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG),
2080 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE),
2082 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE),
2086 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET),
2088 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG),
2090 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG),
2092 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG),
2094 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG),
2111 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE),
2113 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE),
2117 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET),
2126 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base,
2141 return (px_err_panic_handle(rpdip, csr_base, derr,
2144 return (px_err_no_panic_handle(rpdip, csr_base, derr,
2160 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE),
2162 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE),
2166 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET),
2183 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE),
2185 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE),
2189 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET),
2191 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG),
2193 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG),
2211 rx_h1 = CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG);
2212 rx_h2 = CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG);
2213 tx_h1 = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG);
2214 tx_h2 = CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG);
2250 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE),
2252 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE),
2256 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET),
2277 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE),
2279 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE),
2283 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET),