/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
#ifndef _SYS_PX_LIB4U_H
#define _SYS_PX_LIB4U_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Errors returned.
*/
/* no translation exists */
/*
* Register base definitions.
*
* The specific numeric values for CSR, XBUS, Configuration,
* Interrupt blocks and other register bases.
*/
typedef enum {
PX_REG_CSR = 0,
/*
*
* SUN4U px specific data structure.
*/
/* Control block soft state structure */
typedef struct px_cb_list {
} px_cb_list_t;
/* IO chip type */
typedef enum {
PX_CHIP_UNIDENTIFIED = 0,
typedef struct px_cb {
} px_cb_t;
typedef struct pxu {
void *msiq_mapped_p;
/* sun4u specific vars */
/* PCItool */
} pxu_t;
/* cpr_flag */
#define PX_NOT_CPR 0
/*
* Event Queue data structure.
*/
typedef struct eq_rec {
} eq_rec_t;
/*
* EQ record type
*
* Upper 4 bits of eq_rec_fmt_type is used
* to identify the EQ record type.
*/
/* EQ State */
/*
* Default EQ Configurations
*/
#define EQ_1ST_ID 0
/*
* control register decoding
*/
/* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */
/*
* For Fire mmu bypass addresses, bit 43 specifies cacheability.
*/
/*
* For Oberon mmu bypass addresses, bit 47 specifies cacheability.
*/
/*
* The following macros define the address ranges supported for DVMA
* and mmu bypass transfers. For Oberon, bit 63 is used for ordering.
*/
/*
* The following macros are for loading and unloading io tte
* entries.
*/
/* Interrupt states */
#define INTERRUPT_IDLE_STATE 0
/*
* Defines for link width and max packet size for ACKBAK Latency Threshold Timer
* and TxLink Replay Timer Latency Table array sizes
* Num Link Width Packet Size
* 0 1 128
* 1 4 256
* 2 8 512
* 3 16 1024
* 4 - 2048
* 5 - 4096
*/
/*
* Defines for registers which have multi-bit fields.
*/
/* LPU LTSSM states */
/* TLU Control register bits */
/*
* Fire hardware specific version definitions.
* All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20
*/
/*
* Oberon specific definitions.
*/
/*
* HW specific paddr mask.
*/
extern uint64_t px_paddr_mask;
int flags);
/*
* MSIQ Functions:
*/
/*
* MSI Functions:
*/
/*
* MSG Functions:
*/
/*
*/
/*
* Hotplug functions:
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PX_LIB4U_H */