Lines Matching refs:csr_base
291 hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p)
297 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE));
300 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE));
303 CSR_XR(csr_base, IMU_INTERRUPT_STATUS));
306 CSR_XR(csr_base, IMU_ERROR_STATUS_CLEAR));
314 ilu_init(caddr_t csr_base, pxu_t *pxu_p)
320 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE));
323 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE));
326 CSR_XR(csr_base, ILU_INTERRUPT_STATUS));
329 CSR_XR(csr_base, ILU_ERROR_STATUS_CLEAR));
337 tlu_init(caddr_t csr_base, pxu_t *pxu_p)
358 val = CSR_XR(csr_base, TLU_CONTROL);
385 CSR_XS(csr_base, TLU_CONTROL, val);
387 CSR_XR(csr_base, TLU_CONTROL));
400 CSR_XR(csr_base, TLU_STATUS));
406 CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE));
419 CSR_XR(csr_base, TLU_INGRESS_CREDITS_INITIAL));
429 CSR_XR(csr_base, TLU_DIAGNOSTIC));
435 CSR_XR(csr_base, TLU_EGRESS_CREDITS_CONSUMED));
441 CSR_XR(csr_base, TLU_EGRESS_CREDIT_LIMIT));
447 CSR_XR(csr_base, TLU_EGRESS_RETRY_BUFFER));
454 CSR_XR(csr_base, TLU_INGRESS_CREDITS_ALLOCATED));
461 CSR_XR(csr_base, TLU_INGRESS_CREDITS_RECEIVED));
468 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE));
472 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE));
476 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_STATUS));
480 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR));
487 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG));
494 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG));
501 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG));
508 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG));
515 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_SELECT));
522 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ZERO));
528 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ONE));
534 CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_TWO));
541 CSR_XR(csr_base, TLU_DEBUG_SELECT_A));
547 CSR_XR(csr_base, TLU_DEBUG_SELECT_B));
553 CSR_XR(csr_base, TLU_DEVICE_CAPABILITIES));
566 CSR_XS(csr_base, TLU_DEVICE_CONTROL, val);
568 CSR_XR(csr_base, TLU_DEVICE_CONTROL));
574 CSR_XR(csr_base, TLU_DEVICE_STATUS));
580 CSR_XR(csr_base, TLU_LINK_CAPABILITIES));
597 CSR_XS(csr_base, TLU_LINK_CONTROL, val);
599 CSR_XR(csr_base, TLU_LINK_CONTROL));
615 CSR_XR(csr_base, TLU_LINK_STATUS));
632 CSR_XR(csr_base, TLU_SLOT_CAPABILITIES));
639 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE));
647 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE));
654 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS));
661 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR));
668 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG));
675 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG));
682 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG));
689 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG));
702 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE));
709 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE));
716 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS));
723 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_CLEAR));
728 lpu_init(caddr_t csr_base, pxu_t *pxu_p)
740 link_width = CSR_FR(csr_base, TLU_LINK_STATUS, WIDTH);
767 max_payload = ((CSR_FR(csr_base, TLU_CONTROL, CONFIG) &
786 CSR_XR(csr_base, LPU_ID));
797 CSR_XS(csr_base, LPU_RESET, val);
799 CSR_XR(csr_base, LPU_RESET));
811 CSR_XR(csr_base, LPU_DEBUG_STATUS));
817 CSR_XR(csr_base, LPU_DEBUG_CONFIG));
823 CSR_XR(csr_base, LPU_LTSSM_CONTROL));
836 CSR_XR(csr_base, LPU_LINK_STATUS));
842 CSR_XR(csr_base, LPU_INTERRUPT_STATUS));
848 CSR_XR(csr_base, LPU_INTERRUPT_MASK));
855 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_SELECT));
862 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_CONTROL));
869 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1));
876 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1_TEST));
883 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2));
890 CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2_TEST));
903 CSR_XS(csr_base, LPU_LINK_LAYER_CONFIG, val);
905 CSR_XR(csr_base, LPU_LINK_LAYER_CONFIG));
925 CSR_XR(csr_base, LPU_LINK_LAYER_STATUS));
932 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST));
939 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_MASK));
943 CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS));
957 CSR_XS(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL, val);
960 CSR_XR(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL));
972 CSR_XR(csr_base,
987 CSR_XR(csr_base,
1001 CSR_XR(csr_base,
1008 CSR_XS(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, val);
1012 CSR_XR(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD));
1019 CSR_XR(csr_base, LPU_TXLINK_ACKNAK_LATENCY_TIMER));
1025 CSR_XS(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD, val);
1029 CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD));
1035 CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER));
1042 CSR_XR(csr_base, LPU_TXLINK_REPLAY_NUMBER_STATUS));
1049 CSR_XR(csr_base, LPU_REPLAY_BUFFER_MAX_ADDRESS));
1059 CSR_XS(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER, val);
1062 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER));
1069 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_R_W_POINTER));
1076 CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_CREDIT));
1082 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNTER));
1089 CSR_XR(csr_base, LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER));
1100 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR));
1111 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS));
1118 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS));
1124 CSR_XR(csr_base, LPU_TXLINK_TEST_CONTROL));
1135 CSR_XR(csr_base, LPU_TXLINK_MEMORY_ADDRESS_CONTROL));
1142 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD0));
1149 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD1));
1156 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD2));
1163 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD3));
1170 CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD4));
1180 CSR_XR(csr_base, LPU_TXLINK_RETRY_DATA_COUNT));
1191 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_COUNT));
1202 CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA));
1209 CSR_XR(csr_base, LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER));
1220 CSR_XR(csr_base, LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED));
1230 CSR_XR(csr_base, LPU_RXLINK_TEST_CONTROL));
1237 CSR_XR(csr_base, LPU_PHYSICAL_LAYER_CONFIGURATION));
1243 CSR_XR(csr_base, LPU_PHY_LAYER_STATUS));
1250 CSR_XR(csr_base, LPU_PHY_INTERRUPT_AND_STATUS_TEST));
1256 CSR_XR(csr_base, LPU_PHY_INTERRUPT_MASK));
1260 CSR_XR(csr_base, LPU_PHY_LAYER_INTERRUPT_AND_STATUS));
1273 CSR_XR(csr_base, LPU_RECEIVE_PHY_CONFIG));
1279 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS1));
1285 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS2));
1291 CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS3));
1298 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST));
1305 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_MASK));
1309 CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS));
1315 CSR_XR(csr_base, LPU_TRANSMIT_PHY_CONFIG));
1321 CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS));
1328 CSR_XR(csr_base,
1336 CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_MASK));
1340 CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS));
1346 CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS_2));
1360 CSR_XR(csr_base, LPU_LTSSM_CONFIG1));
1371 CSR_XS(csr_base, LPU_LTSSM_CONFIG2, val);
1373 CSR_XR(csr_base, LPU_LTSSM_CONFIG2));
1380 CSR_XS(csr_base, LPU_LTSSM_CONFIG3, val);
1382 CSR_XR(csr_base, LPU_LTSSM_CONFIG3));
1392 CSR_XS(csr_base, LPU_LTSSM_CONFIG4, val);
1394 CSR_XR(csr_base, LPU_LTSSM_CONFIG4));
1400 CSR_XS(csr_base, LPU_LTSSM_CONFIG5, val);
1402 CSR_XR(csr_base, LPU_LTSSM_CONFIG5));
1412 CSR_XR(csr_base, LPU_LTSSM_STATUS1));
1418 CSR_XR(csr_base, LPU_LTSSM_STATUS2));
1425 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS_TEST));
1431 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_MASK));
1435 CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS));
1442 CSR_XR(csr_base, LPU_LTSSM_STATUS_WRITE_ENABLE));
1448 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG1));
1454 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG2));
1460 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG3));
1466 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG4));
1472 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_STATUS));
1479 CSR_XR(csr_base,
1487 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_MASK));
1491 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS));
1498 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN1));
1505 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN2));
1511 CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG5));
1516 dlu_init(caddr_t csr_base, pxu_t *pxu_p)
1520 CSR_XS(csr_base, DLU_INTERRUPT_MASK, 0ull);
1522 CSR_XR(csr_base, DLU_INTERRUPT_MASK));
1525 CSR_XS(csr_base, DLU_LINK_LAYER_CONFIG, val);
1527 CSR_XR(csr_base, DLU_LINK_LAYER_CONFIG));
1532 CSR_XS(csr_base, DLU_FLOW_CONTROL_UPDATE_CONTROL, val);
1534 "0x%llx\n", CSR_XR(csr_base, DLU_FLOW_CONTROL_UPDATE_CONTROL));
1539 CSR_XS(csr_base, DLU_TXLINK_REPLAY_TIMER_THRESHOLD, val);
1542 "0x%llx\n", CSR_XR(csr_base, DLU_TXLINK_REPLAY_TIMER_THRESHOLD));
1547 dmc_init(caddr_t csr_base, pxu_t *pxu_p)
1556 CSR_XS(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val);
1559 CSR_XR(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE));
1566 CSR_XR(csr_base, DMC_CORE_AND_BLOCK_ERROR_STATUS));
1572 CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A, val);
1574 CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A));
1580 CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B, val);
1582 CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B));
1586 hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p)
1590 ilu_init(csr_base, pxu_p);
1591 tlu_init(csr_base, pxu_p);
1595 dlu_init(csr_base, pxu_p);
1598 lpu_init(csr_base, pxu_p);
1606 dmc_init(csr_base, pxu_p);
1613 CSR_XS(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val);
1616 CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE));
1623 CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_STATUS));
1680 mmu_tsb_entries(caddr_t csr_base, pxu_t *pxu_p)
1685 tsb_ctrl = CSR_XR(csr_base, MMU_TSB_CONTROL);
1698 hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p)
1708 obp_tsb_pa = CSR_XR(csr_base, MMU_TSB_CONTROL) & MMU_TSB_PA_MASK;
1710 obp_tsb_entries = mmu_tsb_entries(csr_base, pxu_p);
1723 CSR_XS(csr_base, MMU_TTE_CACHE_INVALIDATE, -1ull);
1738 CSR_XS(csr_base, MMU_TSB_CONTROL, val);
1745 val = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS);
1753 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, val);
1762 (void) CSR_XR(csr_base, MMU_CONTROL_AND_STATUS);
1769 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE));
1772 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE));
1775 CSR_XR(csr_base, MMU_INTERRUPT_STATUS));
1778 CSR_XR(csr_base, MMU_ERROR_STATUS_CLEAR));
2988 px_send_pme_turnoff(caddr_t csr_base)
2992 reg = CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE);
3002 CSR_XS(csr_base, TLU_PME_TURN_OFF_GENERATE, reg);
3014 px_link_wait4l1idle(caddr_t csr_base)
3020 ltssm_state = CSR_FR(csr_base, LPU_LTSSM_STATUS1, LTSSM_STATE);
3033 px_link_retrain(caddr_t csr_base)
3037 reg = CSR_XR(csr_base, TLU_CONTROL);
3044 CSR_BS(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR, LDN_P);
3047 CSR_BS(csr_base, TLU_STATUS, DRAIN);
3050 reg = CSR_XR(csr_base, TLU_CONTROL);
3052 CSR_XS(csr_base, TLU_CONTROL, reg);
3058 px_enable_detect_quiet(caddr_t csr_base)
3062 tlu_ctrl = CSR_XR(csr_base, TLU_CONTROL);
3064 CSR_XS(csr_base, TLU_CONTROL, tlu_ctrl);
3068 oberon_hp_pwron(caddr_t csr_base)
3077 reg = CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE);
3084 if (!CSR_BR(csr_base, TLU_SLOT_CAPABILITIES, HP)) {
3091 reg = CSR_XR(csr_base, TLU_SLOT_STATUS);
3102 CSR_BS(csr_base, HOTPLUG_CONTROL, PWREN);
3106 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD);
3107 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN);
3112 if (!CSR_BR(csr_base, TLU_SLOT_STATUS, PWFD)) {
3118 CSR_BS(csr_base, HOTPLUG_CONTROL, PWREN);
3121 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD);
3122 CSR_BS(csr_base, TLU_SLOT_CONTROL, PWFDEN);
3125 CSR_BS(csr_base, HOTPLUG_CONTROL, CLKEN);
3135 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS);
3136 CSR_XS(csr_base, FLP_PORT_CONTROL, 0x1);
3138 CSR_BC(csr_base, TLU_CONTROL, DRN_TR_DIS);
3139 CSR_BS(csr_base, TLU_DIAGNOSTIC, IFC_DIS);
3140 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST);
3146 CSR_BS(csr_base, HOTPLUG_CONTROL, N_PERST);
3155 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS);
3156 CSR_XS(csr_base, FLP_PORT_CONTROL, 0x20);
3162 reg = CSR_XR(csr_base, DLU_LINK_LAYER_STATUS);
3188 CSR_BC(csr_base, TLU_DIAGNOSTIC, IFC_DIS);
3189 CSR_BS(csr_base, FLP_PORT_ACTIVE_STATUS, TRAIN_ERROR);
3190 CSR_BS(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR, TE_P);
3191 CSR_BS(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR, TE_S);
3192 CSR_BC(csr_base, TLU_CONTROL, DRN_TR_DIS);
3195 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE);
3204 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg);
3210 reg = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES);
3216 CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg);
3219 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3223 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3226 if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON))
3227 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON);
3229 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON);
3238 CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS);
3239 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST);
3242 CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN);
3246 CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN);
3248 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN);
3250 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3254 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3256 CSR_BC(csr_base, TLU_SLOT_STATUS, PWFD);
3265 oberon_hp_pwroff(caddr_t csr_base)
3276 CSR_BS(csr_base, TLU_SLOT_STATUS, PSDC);
3277 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD);
3280 CSR_BS(csr_base, TLU_CONTROL, DRN_TR_DIS);
3284 reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE);
3289 CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg);
3292 reg_tluue = CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE);
3293 reg_tluce = CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE);
3295 CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, 0);
3296 CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, 0);
3299 CSR_BS(csr_base, FLP_PORT_CONTROL, PORT_DIS);
3303 CSR_BC(csr_base, HOTPLUG_CONTROL, N_PERST);
3307 CSR_BC(csr_base, HOTPLUG_CONTROL, CLKEN);
3311 CSR_BC(csr_base, TLU_SLOT_CONTROL, PWFDEN);
3312 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN);
3314 CSR_BS(csr_base, TLU_SLOT_STATUS, PWFD);
3317 CSR_BC(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3);
3320 CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, reg_tluue);
3321 CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, reg_tluce);
3324 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3328 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3331 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3335 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3338 if (CSR_BR(csr_base, HOTPLUG_CONTROL, SLOTPON))
3339 CSR_BC(csr_base, HOTPLUG_CONTROL, SLOTPON);
3341 CSR_BS(csr_base, HOTPLUG_CONTROL, SLOTPON);
3345 while (!(CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3))) {
3359 reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3363 CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
3371 caddr_t csr_base = *(caddr_t *)cookie;
3376 val = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES);
3379 val = CSR_XR(csr_base, TLU_SLOT_CONTROL);
3382 val |= (CSR_XR(csr_base, HOTPLUG_CONTROL) &
3387 val = CSR_XR(csr_base, TLU_SLOT_STATUS);
3390 val = CSR_XR(csr_base, TLU_LINK_CAPABILITIES);
3393 val = CSR_XR(csr_base, TLU_LINK_STATUS);
3407 caddr_t csr_base = *(caddr_t *)cookie;
3420 pwr_state_on = CSR_BR(csr_base, HOTPLUG_CONTROL, PWREN);
3424 ret = oberon_hp_pwron(csr_base);
3426 pwr_fault = CSR_XR(csr_base, TLU_SLOT_STATUS) &
3432 CSR_BC(csr_base, HOTPLUG_CONTROL, PWREN);
3435 ret = oberon_hp_pwroff(csr_base);
3437 CSR_XS(csr_base, TLU_SLOT_CONTROL, val);
3440 CSR_XS(csr_base, TLU_SLOT_STATUS, val);
3487 /* cookie is the csr_base */