Cross Reference: /illumos-gate/usr/src/uts/sun4u/io/px/px

Lines Matching refs:csr_base
182 	caddr_t			xbc_csr_base, csr_base;
218 	csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
242 	hvio_ib_init(csr_base, pxu_p);
243 	hvio_pec_init(csr_base, pxu_p);
244 	hvio_mmu_init(csr_base, pxu_p);
259 		if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3))
266 		px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE);
270 		px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE);
280 	*dev_hdl = (devhandle_t)csr_base;
293 	caddr_t			csr_base;
307 		csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
308 		px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_DISABLE);
1874 	caddr_t	csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
1899 	if (px_send_pme_turnoff(csr_base) != DDI_SUCCESS) {
1950 		if (px_link_wait4l1idle(csr_base) != DDI_SUCCESS) {
2021 	caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
2039 	if (px_link_retrain(csr_base) != DDI_SUCCESS) {
2051 	px_enable_detect_quiet(csr_base);
2381 	caddr_t		csr_base;
2390 	csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
2392 	imu_log_enable = CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE);
2393 	imu_intr_enable = CSR_XR(csr_base, IMU_INTERRUPT_ENABLE);
2410 		CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE,
2413 		CSR_XS(csr_base, IMU_INTERRUPT_ENABLE,
2459 		CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, (imu_log_enable |
2461 		CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, (imu_intr_enable |
2630 	caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
2634 		drain_status = CSR_BR(csr_base, DRAIN_CONTROL_STATUS, DRAIN);
2636 		drain_status = CSR_BR(csr_base, TLU_STATUS, DRAIN);
2646 	caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
2649 	bdf = CSR_BR(csr_base, DMC_PCI_EXPRESS_CONFIGURATION, REQ_ID);
2659 	caddr_t csr_base;
2666 	csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
2669 	*mps = CSR_XR(csr_base, TLU_DEVICE_CAPABILITIES) &
2680 	caddr_t csr_base;
2690 	csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR];
2692 	dev_ctrl = CSR_XR(csr_base, TLU_DEVICE_CONTROL);
2695 	CSR_XS(csr_base, TLU_DEVICE_CONTROL, dev_ctrl);
2697 	link_width = CSR_FR(csr_base, TLU_LINK_STATUS, WIDTH);
2720 	CSR_XS(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD, val);
2726 	CSR_XS(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, val);