Lines Matching refs:csr_base
97 (dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, \
105 (dev_info_t *rpdip, caddr_t csr_base, uint64_t ss_reg, \
119 int px_err_hw_reset_handle(dev_info_t *rpdip, caddr_t csr_base,
122 int px_err_panic_handle(dev_info_t *rpdip, caddr_t csr_base,
125 int px_err_protected_handle(dev_info_t *rpdip, caddr_t csr_base,
128 int px_err_no_panic_handle(dev_info_t *rpdip, caddr_t csr_base,
131 int px_err_no_error_handle(dev_info_t *rpdip, caddr_t csr_base,
156 int px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base,
159 int px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base,
162 int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base,
165 int px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base,
189 int px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base,
192 int px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base,
195 int px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base,
198 int px_err_mmu_parity_handle(dev_info_t *rpdip, caddr_t csr_base,
216 int px_err_wuc_ruc_handle(dev_info_t *rpdip, caddr_t csr_base,
219 int px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base,
222 int px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base,
227 int px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base,
230 int px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base,