Searched refs:cache_line_size (Results 1 - 15 of 15) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/sys/pci/
H A Ddb21554_ctrl.h62 uchar_t cache_line_size; member in struct:db_cfg_state
97 uint8_t cache_line_size; member in struct:db_ctrl
/illumos-gate/usr/src/boot/sys/boot/fdt/dts/arm/
H A Drpi.dts393 cache_line_size = <&vchiq>, "cache-line-size:0";
H A Drpi2.dts404 cache_line_size = <&vchiq>, "cache-line-size:0";
/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dsimba.c232 uchar_t cache_line_size; member in struct:simba_cfg_state
940 statep->cache_line_size =
1034 statep->cache_line_size);
H A Ddb21554.c975 dbp->cache_line_size = ddi_get8(dbp->conf_handle, (uint8_t *)
980 dbp->latency_timer, dbp->cache_line_size);
2352 dbp->cache_line_size);
2359 "\nChild Device Cache Size %x\n", dbp->cache_line_size);
2503 statep->cache_line_size =
2559 statep->cache_line_size);
H A Dpci_pci.c214 uchar_t cache_line_size; member in struct:ppb_cfg_state
/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-regs.h1192 u8 cache_line_size; // 0x0c member in struct:xge_hal_pci_config_le_t
1259 u8 cache_line_size; // 0x0c member in struct:xge_hal_pci_config_t
1315 u8 cache_line_size; // 0x0c
/illumos-gate/usr/src/uts/common/io/cxgbe/common/
H A Dt4_hw.c4104 * @cache_line_size: the host's Cache Line Size
4112 unsigned int cache_line_size)
4116 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
4117 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
4111 t4_fixup_host_params(struct adapter *adap, unsigned int page_size, unsigned int cache_line_size) argument
/illumos-gate/usr/src/uts/intel/io/pci/
H A Dpci_pci.c214 uchar_t cache_line_size; member in struct:__anon9568::__anon9569
/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_dbg.c654 qlge->pci_cfg.cache_line_size = (uint8_t)
731 qlge->pci_cfg.cache_line_size);
H A Dqlge.c6027 (knp++)->value.ui32 = qlge->pci_cfg.cache_line_size;
/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-mgmtaux.c1189 __HAL_AUX_ENTRY("cache_line_size",
1190 pci_config.cache_line_size, "0x%02X");
/illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/qlge/
H A Dqlge_hw.h1020 volatile uint8_t cache_line_size; member in struct:__anon7814
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h1613 u8_t cache_line_size; member in struct:_lm_hardware_info_t
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_devinfo.c322 pdev->hw_info.cache_line_size = (u8_t) val;

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