bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * CDDL HEADER START
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * The contents of this file are subject to the terms of the
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Common Development and Distribution License (the "License").
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * You may not use this file except in compliance with the License.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * or http://www.opensolaris.org/os/licensing.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * See the License for the specific language governing permissions
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * and limitations under the License.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * When distributing Covered Code, include this CDDL HEADER in each
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * If applicable, add the following below this CDDL HEADER, with the
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * fields enclosed by brackets "[]" replaced with your own identifying
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * information: Portions Copyright [yyyy] [name of copyright owner]
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * CDDL HEADER END
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan * Copyright 2010 QLogic Corporation. All rights reserved.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MB_DATA_REG_COUNT (MB_REG_COUNT-1)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_SCHULTZ(qlge) ((qlge)->device_id == ISP_SCHULTZ)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Data bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan /* software statics */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan /* statics by hw */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Register Definitions...
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* System Register 0x00 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define PROC_ADDR_FUNC0_MBO (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define PROC_ADDR_FUNC2_MBO (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* System Register 0x08 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SYSTEM_EFE_FAE_MASK (SYSTEM_EFE_FAE<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * There are no values defined as of edit #15.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Reset/Failover Register (RST_FO) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Function Specific Control Register (FSC) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Host Command Status Register (CSR) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * There are no valued defined as of edit #15.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define CSR_CMD_CLR_R2PCI_INT 0xa0000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Configuration Register (CFG) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Status Register (STS) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Register (REV_ID) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Error Status Register (ERR_STS) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Semaphore Register (SEM) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Stop CQ Processing Register (CQ_STOP) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_ADDR_TYPE_MULTI_MAC 0x00010000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_ADDR_TYPE_MULTI_FLTR 0x00030000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_ADDR_TYPE_MGMT_MAC 0x00050000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_ADDR_TYPE_MGMT_VLAN 0x00060000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_ADDR_TYPE_MGMT_TU_DP 0x00090000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * MAC Protocol Address Index Register (SPLT_HDR, 0xC0) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan NIC_RCV_CFG_DFQ = 0 /* HARDCODE default queue to 0. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Routing Index Register (RT_IDX) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Nic Queue format - type 2 bits */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Hierarchy for the NIC Queue Mask */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Reset/Failover Register 0C */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FUNCTION_RESET_MASK (FUNCTION_RESET<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Function Specific Control Register 0x10 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Configuration Register 0x28 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Semaphore Register (SEM) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* System Register 0x08 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SYSTEM_EFE_FAE_MASK (SYSTEM_EFE_FAE<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Interrupt Status Register-1 0x3C */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Processor Address Register 0x00 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define PROCESSOR_ADDRESS_RDY (0x8000u<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define PROCESSOR_ADDRESS_READ (0x4000u<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Host Command/Status Register 0x14 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_SET_RISC_RESET 0x10000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_CLEAR_RISC_RESET 0x20000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_SET_RISC_PAUSE 0x30000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_RELEASE_RISC_PAUSE 0x40000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_SET_RISC_INTR 0x50000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_CLEAR_RISC_INTR 0x60000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_SET_PARITY_ENABLE 0x70000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_FORCE_BAD_PARITY 0x80000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_RELEASE_BAD_PARITY 0x90000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define HOST_CMD_CLEAR_RISC_TO_HOST_INTR 0xA0000000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Semaphor Register 0x64 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PORT0_XGMAC_SEM_BITS (QL_SEM_BITS_BASE_CODE)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PORT1_XGMAC_SEM_BITS (QL_SEM_BITS_BASE_CODE << 2)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_ICB_ACCESS_ADDRESS_SEM_BITS (QL_SEM_BITS_BASE_CODE << 4)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_MAC_PROTOCOL_SEM_BITS (QL_SEM_BITS_BASE_CODE << 6)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_FLASH_SEM_BITS (QL_SEM_BITS_BASE_CODE << 8)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PROBE_MUX_SEM_BITS (QL_SEM_BITS_BASE_CODE << 10)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_ROUTING_INDEX_SEM_BITS (QL_SEM_BITS_BASE_CODE << 12)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PROCESSOR_SEM_BITS (QL_SEM_BITS_BASE_CODE << 14)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_NIC_RECV_CONFIG_SEM_BITS (QL_SEM_BITS_BASE_CODE << 14)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PORT0_XGMAC_SEM_MASK (QL_SEM_MASK_BASE_CODE)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PORT1_XGMAC_SEM_MASK (QL_SEM_MASK_BASE_CODE << 2)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_ICB_ACCESS_ADDRESS_SEM_MASK (QL_SEM_MASK_BASE_CODE << 4)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_MAC_PROTOCOL_SEM_MASK (QL_SEM_MASK_BASE_CODE << 6)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_FLASH_SEM_MASK (QL_SEM_MASK_BASE_CODE << 8)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PROBE_MUX_SEM_MASK (QL_SEM_MASK_BASE_CODE << 10)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_ROUTING_INDEX_SEM_MASK (QL_SEM_MASK_BASE_CODE << 12)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_PROCESSOR_SEM_MASK (QL_SEM_MASK_BASE_CODE << 14)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QL_NIC_RECV_CONFIG_SEM_MASK (QL_SEM_MASK_BASE_CODE << 14)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* XGMAC Address Register 0x78 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define XGMAC_ADDRESS_READ_TRANSACT (0x4000u<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define XGMAC_ADDRESS_ACCESS_ERROR (0x2000u<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* XGMAC Register Set */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_GLOBAL_CONFIGURATION 0x108
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_TX_CONFIGURATION 0x10C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_RX_CONFIGURATION 0x110
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_TX_MULTCAST_PKTS 0x210
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_TX_BROADCAST_PKTS 0x218
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_TX_PAUSE_PKTS 0x230
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_RX_BROADCAST_PKTS 0x320
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_RX_MULTCAST_PKTS 0x328
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_RX_JABBER_PKTS 0x348
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_RX_PAUSE_PKTS 0x388
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_XGMAC_MAC_RX_FIFO_DROPS 0x5B8
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* MAC Protocol Address Index Register Set 0xA8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_PROTOCOL_ADDRESS_INDEX_MW (0x8000u<<16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_PROTOCOL_ADDRESS_ENABLE (1 << 27)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_PROTOCOL_TYPE_MULTICAST (0x10000u)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* NIC Receive Configuration Register 0xD4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RECV_CONFIG_DEFAULT_Q_MASK (0x7F000000u)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RECV_CONFIG_VTAG_REMOVAL_MASK (0x80000u)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_1024_TO_1518_PKT_LO 0x00000264
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define STAT_CNT_CTL_CLEAR_TX (1 << 0) /* Control */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define STAT_CNT_CTL_CLEAR_RX (1 << 1) /* Control */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_UNDERSIZE_FCERR_PKTS 0x00000350
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_UNDERSIZE_FCERR_PKTS_LO 0x00000354
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_512_TO_1023_PKTS_LO 0x000003b4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_1024_TO_1518_PKTS_LO 0x000003bc
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_1519_TO_MAX_PKTS_LO 0x000003c4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES0_LO 0x00000504
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES1_LO 0x0000050C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES2_LO 0x00000514
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES3_LO 0x0000051C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES4_LO 0x00000524
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES5_LO 0x0000052C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES6_LO 0x00000534
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_CBFC_PAUSE_FRAMES7_LO 0x0000053C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES0_LO 0x0000056C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES1_LO 0x00000574
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES2_LO 0x0000057C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES3_LO 0x00000584
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES4_LO 0x0000058C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES5_LO 0x00000594
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES6_LO 0x0000059C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_CBFC_PAUSE_FRAMES7_LO 0x000005A4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY0_LO 0x00000644
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY1_LO 0x0000064C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY2_LO 0x00000654
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY3_LO 0x0000065C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY4_LO 0x00000664
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY5_LO 0x0000066C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY6_LO 0x00000674
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_OCTETS_PRIORITY7_LO 0x0000067C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY0_LO 0x000006C4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY1_LO 0x000006CC
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY2_LO 0x000006D4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY3_LO 0x000006DC
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY4_LO 0x000006E4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY5_LO 0x000006EC
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY6_LO 0x000006F4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_OCTETS_PRIORITY7_LO 0x000006FC
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY0_LO 0x00000704
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY1_LO 0x0000070C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY2_LO 0x00000714
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY3_LO 0x0000071C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY4_LO 0x00000724
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY5_LO 0x0000072C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY6_LO 0x00000734
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_DISCARD_PRIORITY7_LO 0x0000073C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Routing Index Register 0xE4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ROUTING_INDEX_DEFAULT_ENABLE_MASK (0x8320000u)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ROUTING_INDEX_DEFAULT_DISABLE_MASK (0x0320000u)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Routing Data Register 0xE8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ROUTE_AS_BCAST_MCAST_MATCH 0x8000u
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ROUTE_AS_VALID_PKT 0x800000u /* promiscuous mode? */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * General definitions...
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Below are a number compiler switches for controlling driver behavior.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Some are not supported under certain conditions and are notated as such.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* MTU & Frame Size stuff */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define NORMAL_FRAME_SIZE 2500 /* ETHERMTU,1500 */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define LRG_BUF_NORMAL_SIZE NORMAL_FRAME_SIZE
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define LRG_BUF_JUMBO_SIZE JUMBO_FRAME_SIZE
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define VLAN_HEADER_LEN sizeof (struct ether_vlan_header) /* 18 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ETHER_HEADER_LEN sizeof (struct ether_header) /* 14 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RX_TX_RING_SHADOW_SPACE 2 /* 1st one is wqicb and 2nd for cqicb */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define BUF_Q_PTR_SPACE ((((NUM_SMALL_BUFFERS * sizeof (uint64_t)) \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan (((NUM_LARGE_BUFFERS * sizeof (uint64_t)) \
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_RX_COALESCE_WAIT 90 /* usec wait for coalescing */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_RX_INTER_FRAME_WAIT 30 /* max interframe-wait for */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan /* coalescing */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_TX_COALESCE_WAIT 90 /* usec wait for coalescing */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_TX_INTER_FRAME_WAIT 30 /* max interframe-wait for */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan /* coalescing */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_RX_COALESCE_WAIT_JUMBO 40 /* usec wait for coalescing */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_RX_INTER_FRAME_WAIT_JUMBO 10 /* max interframe-wait for */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan /* coalescing */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_TX_COALESCE_WAIT_JUMBO 40 /* usec wait for coalescing */
accf27a5824ae84dfac7b089c4325917231a7d15Sukumar Swaminathan#define DFLT_TX_INTER_FRAME_WAIT_JUMBO 10 /* max interframe-wait for */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan /* coalescing */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define DFLT_PAYLOAD_COPY_THRESH 6 /* must be at least 6 usec */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Large & Small Buffers for Receives
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Link must be in one of these states */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* qlge->flags definitions. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * ISP PCI Configuration Register Set structure definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef volatile struct
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t pci_cntl_reg_set_mem_base_address_lower;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t pci_cntl_reg_set_mem_base_address_upper;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t pci_doorbell_mem_base_address_lower;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t pci_doorbell_mem_base_address_upper;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Schultz Control Registers Index
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_FUNCTION_SPECIFIC_CONTROL 0x10
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_ICB_ACCESS_ADDRESS_LOWER 0x20
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_ICB_ACCESS_ADDRESS_UPPER 0x24
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define INTR_EN_IHD_MASK (INTR_EN_IHD << 16)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_NIC_ENHANCED_TX_SCHEDULE 0x80
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_CNA_ENHANCED_TX_SCHEDULE 0x84
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_WQ_PAGE_TABLE_BASE_ADDR_LOWER 0x98
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_WQ_PAGE_TABLE_BASE_ADDR_UPPER 0x9C
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_CQ_PAGE_TABLE_BASE_ADDR_LOWER 0xA0
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_CQ_PAGE_TABLE_BASE_ADDR_UPPER 0xA4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_MAC_PROTOCOL_ADDRESS_INDEX 0xA8
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REG_NIC_RECEIVE_CONFIGURATION 0xD4
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define INTR_MASK_LINK_IRQS = (INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Interrupt Enable Register 0x34 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_ENABLE_INTR(qlge) ql_put32(qlge, \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_DISABLE_INTR(qlge) ql_put32(qlge, \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_ENABLE_PI_INTR(qlge) ql_put32(qlge, \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_DISABLE_PI_INTR(qlge) ql_put32(qlge, \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_ENABLE_GLOBAL_INTRS(qlge) { \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_DISABLE_GLOBAL_INTRS(qlge) { \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Mailbox Registers
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FUNC_0_IN_MAILBOX_0_REG_OFFSET 0x1180
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FUNC_0_OUT_MAILBOX_0_REG_OFFSET 0x1190
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FUNC_1_IN_MAILBOX_0_REG_OFFSET 0x1280
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FUNC_1_OUT_MAILBOX_0_REG_OFFSET 0x1290
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Control Register Set definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef volatile struct
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t processor_address; /* 0x00 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t processor_data; /* 0x04 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t system_data; /* 0x08 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t reset_failover; /* 0x0C */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t function_specific_control; /* 0x10 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t host_command_status; /* 0x14 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t idb_access_address_low; /* 0x20 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t idb_access_address_high; /* 0x24 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t configuration; /* 0x28 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t interrupt_enable; /* 0x34 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t interrupt_mask; /* 0x38 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t interrupt_status_1; /* 0x3c */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t interrupt_status_2; /* 0x40 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t interrupt_status_3; /* 0x44 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t interrupt_status_4; /* 0x48 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t force_ecc_error; /* 0x50 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t error_status; /* 0x54 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t internal_ram_debug_address; /* 0x58 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t internal_ram_data; /* 0x5c */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t correctable_ecc_error; /* 0x60 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t xgmac_address; /* 0x78 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t nic_enhanced_tx_schedule; /* 0x80 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t cna_enhanced_tx_schedule; /* 0x84 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t flash_address; /* 0x88 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t page_table_rid; /* 0x94 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t wq_page_table_base_address_lower; /* 0x98 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t wq_page_table_base_address_upper; /* 0x9c */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t cq_page_table_base_address_lower; /* 0xA0 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t cq_page_table_base_address_upper; /* 0xA4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t mac_protocol_address_index; /* 0xA8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t mac_protocol_data; /* 0xAc */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t cos_default_cq_reg1; /* 0xB0 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t cos_default_cq_reg2; /* 0xB4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t ethertype_skip_reg1; /* 0xB8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t ethertype_skip_reg2; /* 0xBC */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t split_header; /* 0xC0 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t fcoe_pause_threshold; /* 0xC4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t nic_pause_threshold; /* 0xC8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t fc_ethertype; /* 0xCC */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t fcoe_recv_configuration; /* 0xD0 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t nic_recv_configuration; /* 0xD4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t cos_tags_in_fcoe_fifo; /* 0xD8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t cos_tags_in_nic_fifo; /* 0xDc */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t mgmt_recv_configuration; /* 0xE0 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t routing_index; /* 0xE4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t routing_data; /* 0xE8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t xg_serdes_address; /* 0xF0 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t xg_serdes_data; /* 0xF4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t probe_mux_address; /* 0xF8 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvolatile uint32_t probe_mux_read_data; /* 0xFc */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define INTR_PENDING (uint32_t)(CSR_COMPLETION_INTR)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef volatile struct
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan volatile uint32_t doorbell_reg_address[256]; /* 0x00 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SET_RMASK(val) ((val & 0xffff) | (val << 16))
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * DMA registers read only
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef volatile struct
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define DMAREGS_SIZE (sizeof (iop_dmaregs_t))
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint8_t card_serial_num[16]; /* 38 - 47 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t time_of_crash_in_secs; /* 48 - 4B */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t time_of_crash_in_ms; /* 4C - 4F */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint16_t outb_risc_sd_num_frames; /* 50 - 51 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint16_t iap_sd_num_frames; /* 54 - 55 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint16_t inb_risc_sd_length; /* 56 - 57 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint8_t outb_risc_reg_dump[256]; /* 80 -17F */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint8_t inb_risc_reg_dump[256]; /* 180 -27F */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint8_t inb_outb_risc_stack_dump[1]; /* 280 - ??? */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * I/O register access macros
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * #if QL_DEBUG & 1
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan ddi_get8(qlge->dev_handle, (uint8_t *)addr)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan ddi_get32(qlge->dev_handle, (uint32_t *)addr)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan ddi_put8(qlge->dev_handle, (uint8_t *)addr, data)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan ddi_put16(qlge->dev_handle, (uint16_t *)addr, data)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define WRT_REG_DWORD(qlge, addr, data) \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan ddi_put32(qlge->dev_handle, (uint32_t *)addr, data)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * QLGE-specific ioctls ...
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_IOC ((((('Q' << 8) + 'L') << 8) + 'A') << 8)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Definition of ioctls commands
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_PCI_STATUS (QLA_IOC|1) /* Read all PCI registers */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_READ_CONTRL_REGISTERS (QLA_IOC|8)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_MANUAL_READ_FLASH (QLA_IOC|9)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_MANUAL_WRITE_FLASH (QLA_IOC|10)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_SUPPORTED_DUMP_TYPES (QLA_IOC|11)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_GET_BINARY_CORE_DUMP (QLA_IOC|12)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_TRIGGER_SYS_ERROR_EVENT (QLA_IOC|13)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_LIST_ADAPTER_INFO (QLA_IOC|20)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_WRITE_FW_IMAGE_HEADERS (QLA_IOC|22)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_CONTINUE_COPY_IN (QLA_IOC|29)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_CONTINUE_COPY_OUT (QLA_IOC|30)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_IOCTL_CMD_FIRST QLA_PCI_STATUS
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QLA_IOCTL_CMD_LAST QLA_SOFT_RESET
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Solaris IOCTL can copy in&out up to 1024 bytes each time */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IOCTL_MAX_BUF_SIZE (IOCTL_BUFFER_SIZE*512) /* 512k */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IOCTL_HEADER_LEN sizeof (ioctl_header_info_t)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IOCTL_MAX_DATA_LEN (IOCTL_BUFFER_SIZE - IOCTL_HEADER_LEN)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint16_t addr; /* register number [0..ff] */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint16_t value; /* data to write/data read */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t addr; /* address to write/data read */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t value; /* data to write/data read */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t addr; /* register number [0..ff] */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t size; /* number of data to write/data read */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanstruct qlnic_mpi_version_info mpi_version; /* MPI Version */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanstruct qlnic_link_status_info link_status; /* Link Status */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t pci_binding; /* /bus/dev/func number per IEEE 1277 format */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define DUMP_DESCRIPTION_HEADER_SIGNATURE 0x42535451 /* "QTSB" */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define DUMP_IMAGE_HEADER_SIGNATURE 0x504D4451 /* "QDMP" */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* utility request */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define DUMP_DESCRIPTION_FOOTER_SIGNATURE 0x45535451 /* "QTSE" */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Solaris qlnic exit status.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_OK QN_ERR_BASE | 0 /* Success */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_NOT_SUPPORTED QN_ERR_BASE | 1 /* Command not supported */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_INVALID_PARAM QN_ERR_BASE | 2 /* Invalid parameter */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_WRONG_NO_PARAM QN_ERR_BASE | 3 /* Wrong number of parameters */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_FILE_NOT_FOUND QN_ERR_BASE | 4 /* File not found */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_FILE_READ_ERR QN_ERR_BASE | 5 /* File read err */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_FILE_WRITE_ERR QN_ERR_BASE | 6 /* File write err */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define QN_ERR_NO_MEMORY QN_ERR_BASE | 7 /* No Memory */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_NIC_BOOT_CODE_SIZE 0x80000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_MPI_RISC_FW_ADDR 0x100000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_MPI_RISC_FW_SIZE 0x10000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_NIC_PARAM0_ADDR 0x140200
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_NIC_PARAM1_ADDR 0x140600
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_EDC_PHY_FW_ADDR 0x170000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_FC_BOOT_CODE_ADDR 0x200000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_FC_BOOT_CODE_SIZE 0x80000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_FC_BOOT_CODE_ADDR 0x200000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_FC_BOOT_CODE_SIZE 0x80000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* flash region for testing */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_WIN_FW_DUMP0_ADDR 0x190000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_WIN_FW_DUMP0_SIZE 0x30000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_FLASH_TEST_REGION_ADDR ISP_8100_WIN_FW_DUMP0_ADDR
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ISP_8100_FLASH_TEST_REGION_SIZE 0x10000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAILBOX_TOV 30 /* Default Timeout value. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * ISP mailbox commands from Host
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_NO_OPERATION 0 /* No Operation. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_MAILBOX_REGISTER_TEST 6 /* Mailbox echo test */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_ABOUT_FIRMWARE 8 /* About Firmware. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_RISC_MEMORY_COPY 0xA /* Copy RISC memory. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_LOAD_RISC_RAM 0xB /* Load RISC RAM command. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_DUMP_RISC_RAM 0xC /* Dump RISC RAM command. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_READ_RAM_WORD 0xF /* Read RAM */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_GENERATE_SYS_ERROR 0x2A /* Generate System Error */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_WRITE_SFP 0x30 /* Write SFP. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_READ_SFP 0x31 /* Read SFP. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_GET_INIT_CTRL_BLOCK 0x61 /* Get Initialization CBLK */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_IDC_REQUEST 0x100 /* IDC Request. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IDC_REQ_ALL_DEST_FUNC_MASK BIT_4 /* Mailbox 1 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IDC_REQ_DEST_FUNC_0_MASK BIT_0 /* Mailbox 2 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_IDC_ACK 0x101 /* IDC Acknowledge. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_IDC_TIME_EXTENDED 0x102 /* IDC Time Extended. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_SET_WAKE_ON_LANE_FILTER 0x111
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_CLEAR_WAKE_ON_LANE_FILTER 0x112
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_SET_WAKE_ON_LANE_MAGIC_PKT 0x113
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBC_CLEAR_WAKE_ON_LANE_MAGIC_PKT 0x114
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ENABLE_JUMBO_FRAME_SIZE_MASK BIT_16
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * ISP mailbox command complete status codes
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBS_COMMAND_PARAMETER_ERROR 0x4006
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Async Event Status */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBA_IDC_INTERMEDIATE_COMPLETE 0x1000
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBA_IDC_REQUEST_NOTIFICATION 0x8101
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBA_SFT_TRANSCEIVER_INSERTION 0x8130
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBA_SFT_TRANSCEIVER_REMOVAL 0x8131
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MBA_FIRMWARE_INIT_COMPLETE 0x8400
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef struct phy_firmware_version_info {
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan PAUSE_MODE_STANDARD, /* Standard Ethernet Pause */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan PAUSE_MODE_PER_PRIORITY /* Class Based Pause */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Mailbox command parameter structure definition. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t from_mpi; /* number of Incomming from MPI to driver */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanclock_t timeout; /* Timeout in seconds. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Returned Mailbox registers. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t from_mpi; /* number of Incomming from MPI to driver */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Address/Length pairs for the coredump. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* 64 probes, 8 bytes per probe + 4 bytes to list the probe ID */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define PROBE_DATA_LENGTH_WORDS ((64 * 2) + 1)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) + \
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Save both the address and data register */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef struct mpi_coredump_global_header {
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef struct mpi_coredump_segment_header {
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_global_header_t mpi_global_header;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t core_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t mpi_core_regs[MPI_CORE_REGS_CNT];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t test_logic_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t rmii_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t fcmac1_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t fcmac2_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t fc1_mbx_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t ide_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t nic1_mbx_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t nic1_mbx_regs[NIC_MBX_REGS_CNT];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t smbus_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t fc2_mbx_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t nic2_mbx_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t nic2_mbx_regs[NIC_MBX_REGS_CNT];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t i2c_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t memc_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t pbus_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t mde_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xaui_an_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xaui_hss_pcs_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xfi_an_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xfi_train_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xfi_hss_pcs_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xfi_hss_tx_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xfi_hss_rx_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xfi_hss_pll_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t nic_regs_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* one interrupt state for each CQ */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t intr_states_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t xgmac_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t probe_dump_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t probe_dump[PROBE_DATA_LENGTH_WORDS * NUMBER_OF_PROBES];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t routing_reg_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t routing_regs[NUMBER_ROUTING_REG_ENTRIES * WORDS_PER_ROUTING_REG_ENTRY];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t mac_prot_reg_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanuint32_t mac_prot_regs[MAC_PROTOCOL_REGISTER_WORDS * WORDS_PER_MAC_PROT_ENTRY];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t ets_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t code_ram_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanmpi_coredump_segment_header_t memc_ram_seg_hdr;
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define WCS_MPI_CODE_RAM_LENGTH (0x2000*4)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Force byte packing for the following structures */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Work Queue (Request Queue) Initialization Control Block (WQICB)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Completion Queue (Response Queue) Initialization Control Block (CQICB)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint32_t cq_base_addr_lo; /* completion queue base address */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint32_t prod_idx_addr_lo; /* completion queue host copy */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan /* producer index host shadow */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Host Command IOCB Formats
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * The following constants define control bits for buffer
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * length fields for all IOCB's.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* 32 words, 128 bytes */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define TX_DESC_PER_IOCB 8 /* Number of descs in one TX IOCB */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_D 0x08 /* disable generation of comp. msg */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_I 0x02 /* disable generation of intr at comp */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_TC 0x80 /* enable TCP checksum offload */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_UC 0x40 /* enable UDP checksum offload */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_LSO 0x20 /* enable LSO offload */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_VLAN_OFFSET_MASK 0xF8 /* VLAN TCI insert */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_V 0x04 /* insert VLAN TCI */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_DFP 0x02 /* Drop for Failover port */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_REQ_IC 0x01 /* enable IP checksum offload */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint32_t frame_len; /* max 9000,for none LSO, 16M for LSO */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint16_t hdr_off; /* tcp/udp hdr offset */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan struct oal_entry oal_entry[TX_DESC_PER_IOCB]; /* max FFFFF 1M bytes */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* 16 words, 64 bytes */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_VLAN_ID_MASK 0xFFF
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* 16 words, 64 bytes */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SYS_EVENT_MGMT_FATAL_ERR 0x8 /* MPI_PROCESSOR */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SYS_EVENT_PCI_ERR_READING_SML_LRG_BUF 0x40
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Status Register (#define STATUS) bit definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Generic Response Queue IOCB Format which abstracts the difference between
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * IB_MAC, OB_MAC IOCBs
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Restore original packing rules */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define RESPONSE_ENTRY_SIZE (sizeof (struct net_rsp_iocb))
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define REQUEST_ENTRY_SIZE (sizeof (struct ob_mac_iocb_req))
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Little endian machine correction defines. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define BIG_ENDIAN_16(x) ql_change_endian((uint8_t *)x, 2)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define BIG_ENDIAN_24(x) ql_change_endian((uint8_t *)x, 3)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define BIG_ENDIAN_32(x) ql_change_endian((uint8_t *)x, 4)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define BIG_ENDIAN_64(x) ql_change_endian((uint8_t *)x, 8)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define BIG_ENDIAN(bp, bytes) ql_change_endian((uint8_t *)bp, bytes)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#endif /* _LITTLE_ENDIAN */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Big endian machine correction defines. */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define LITTLE_ENDIAN_16(x) ql_change_endian((uint8_t *)x, 2)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define LITTLE_ENDIAN_24(x) ql_change_endian((uint8_t *)x, 3)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define LITTLE_ENDIAN_32(x) ql_change_endian((uint8_t *)x, 4)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define LITTLE_ENDIAN_64(x) ql_change_endian((uint8_t *)x, 8)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define LITTLE_ENDIAN(bp, bytes) ql_change_endian((uint8_t *)bp, bytes)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#endif /* _BIG_ENDIAN */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathanvoid ql_change_endian(uint8_t *, size_t);
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Flash Address Register 0x88 */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Flash definitions.
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint32_t flash_size; /* length in bytes of flash */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint32_t sec_mask; /* sector number mask */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint8_t flash_manuf; /* flash chip manufacturer id */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint8_t flash_cap; /* flash chip capacity */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan * Flash Description Table
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FLASH_DESC_VAILD 0x44494C51 /* "QLID" */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint16_t flash_len; /* flash description table length */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* flash manufacturer id's */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define AMD_FLASH 0x01 /* AMD / Spansion */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ST_FLASH 0x20 /* ST Electronics */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SST_FLASH 0xbf /* SST Electronics */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MXIC_FLASH 0xc2 /* Macronix (MXIC) */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ATMEL_FLASH 0x1f /* Atmel (AT26DF081A) */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define WINBOND_FLASH 0xef /* Winbond (W25X16,W25X32) */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define INTEL_FLASH 0x89 /* Intel (QB25F016S33B8) */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* flash id defines */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define AMD_FLASHID_128K 0x6e /* 128k AMD flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define AMD_FLASHID_512K 0x4f /* 512k AMD flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define AMD_FLASHID_512Kt 0xb9 /* 512k AMD flash chip - top boot blk */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define AMD_FLASHID_512Kb 0xba /* 512k AMD flash chip - btm boot blk */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define AMD_FLASHID_1024K 0x38 /* 1 MB AMD flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ST_FLASHID_128K 0x23 /* 128k ST flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ST_FLASHID_512K 0xe3 /* 512k ST flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ST_FLASHID_M25PXX 0x20 /* M25Pxx ST flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SST_FLASHID_128K 0xd5 /* 128k SST flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SST_FLASHID_1024K 0xd8 /* 1 MB SST flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SST_FLASHID_1024K_A 0x80 /* 1 MB SST 25LF080A flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SST_FLASHID_1024K_B 0x8e /* 1 MB SST 25VF080B flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SST_FLASHID_2048K 0x25 /* 2 MB SST 25VF016B flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MXIC_FLASHID_512K 0x4f /* 512k MXIC flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MXIC_FLASHID_1024K 0x38 /* 1 MB MXIC flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define MXIC_FLASHID_25LXX 0x20 /* 25Lxx MXIC flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ATMEL_FLASHID_1024K 0x45 /* 1 MB ATMEL flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define SPAN_FLASHID_2048K 0x02 /* 2 MB Spansion flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define WINBOND_FLASHID 0x30 /* Winbond W25Xxx flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define INTEL_FLASHID 0x89 /* Intel QB25F016S33B8 flash chip */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* flash type defines */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FLASH_LEGACY (FLASH128 | FLASH512S)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FLASH_FIRMWARE_IMAGE_ADDR 0x100000 /* 1M */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef struct {
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef struct {
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint8_t imagelength[2]; /* In sectors */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Flash Layout Table Data Structure(FLTDS) */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FLASH_FLTDS_SIGNATURE 0x544C4651 /* "QFLT" */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Image Layout Table Data Structure(ILTDS) */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FLASH_ILTDS_SIGNATURE 0x4D494651 /* "QFIM" */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint16_t table_version; /* version of this structure */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint16_t length; /* length of the table */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint16_t number_entries; /* Number of type/len/size entries */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint16_t version; /* version of the image */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IMAGE_TABLE_HEADER_LEN sizeof (ql_iltds_header_t)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ILTDS_REGION_VERSION_LEN_NA 0 /* version not applicable */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ILTDS_IMG_SWAP_NONE 0 /* no swap needed */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ILTDS_IMG_CARD_TYPE_ALL 0 /* apply to all types */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ILTDS_IMG_CARD_TYPE_SR 1 /* apply to SR/fc cards */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ILTDS_IMG_CARD_TYPE_COPPER 2 /* apply to Copper cards */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ILTDS_IMG_CARD_TYPE_MEZZ 4 /* apply to Mezz cards */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IMAGE_TABLE_ENTRY_LEN sizeof (ql_iltds_img_entry_t)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IMAGE_TABLE_TIME_STAMP_LEN sizeof (ql_iltds_time_stamp_t)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define IMAGE_TABLE_IMAGE_DEFAULT_ENTRIES 5
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathantypedef struct ql_iltds_description_header {
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan ql_iltds_img_entry_t img_entry[IMAGE_TABLE_IMAGE_DEFAULT_ENTRIES];
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define ILTDS_DESCRIPTION_HEADERS_LEN sizeof (ql_iltds_description_header_t)
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* flash layout table definition */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan uint16_t length; /* length of the flt table,no table header */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* table entry */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* flt table */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan/* Nic Configuration Table */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#define FLASH_NIC_CONFIG_SIGNATURE 0x30303038 /* "8000" */
bafec74292ca6805e5acb387856f4e60a5314b37Sukumar Swaminathan#endif /* _QLGE_HW_H */