/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*
* Copyright (c) 2002-2006 Neterion, Inc.
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef XGE_HAL_REGS_H
#define XGE_HAL_REGS_H
typedef struct {
/* General Control-Status Registers */
/* XGXS must be removed from reset only once. */
/* The SW_RESET register must read this value after a successful reset. */
#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
#else
#endif
/* PCI-X Controller registers */
/*
#define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
#define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
#define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
*/
/* PIC Control registers */
/* Automated statistics collection */
/* General Configuration */
/* TxDMA registers */
/* TxDMA arbiter */
/* Tx FIFO controller */
/* Tx Protocol assist */
/* Recent add, used only debug purposes. */
/* RxDMA Registers */
/* DMA arbiter */
/* Per-ring controller regs */
/* Receive traffic interrupts */
/* Media Access Controller Register */
#define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0
/*
u64 rmac_addr_cfg;
#define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
#define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
#define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48
#define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
*/
/* rx traffic steering */
/* memory controller registers */
/* MC configuration */
/* XGXG */
/* XGXS control registers */
/* Using this strcture to calculate offsets */
typedef struct xge_hal_pci_config_le_t {
typedef struct xge_hal_pci_config_t {
#ifdef XGE_OS_HOST_BIG_ENDIAN
#else
#endif
#endif /* XGE_HAL_REGS_H */