/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 QLogic Corporation. All rights reserved.
*/
#ifndef _QLGE_HW_H
#define _QLGE_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Data bit definitions.
*/
typedef struct ql_stats
{
/* software statics */
/* TX */
/* RX */
/* statics by hw */
/*
* Register Definitions...
*/
/* System Register 0x00 */
/* System Register 0x08 */
enum {
/*
* There are no values defined as of edit #15.
*/
};
/*
*/
/*
* Function Specific Control Register (FSC) bit definitions.
*/
enum {
};
/*
* Host Command Status Register (CSR) bit definitions.
*/
/*
* There are no valued defined as of edit #15.
*/
/*
* Configuration Register (CFG) bit definitions.
*/
enum {
};
/*
* Status Register (STS) bit definitions.
*/
enum {
};
/*
* Register (REV_ID) bit definitions.
*/
enum {
REV_ID_NICROLL_SHIFT = 0,
};
/*
* Force ECC Error Register (FRC_ECC_ERR) bit definitions.
*/
enum {
};
/*
* Error Status Register (ERR_STS) bit definitions.
*/
enum {
};
/*
* Semaphore Register (SEM) bit definitions.
*/
/*
* Example:
* reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
*/
#define SEM_CLEAR 0
#define SEM_XGMAC0_SHIFT 0
/*
* Stop CQ Processing Register (CQ_STOP) bit definitions.
*/
enum {
};
/*
* MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
*/
/*
* MAC Protocol Address Index Register (SPLT_HDR, 0xC0) bit definitions.
*/
/*
* NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
*/
enum {
};
/*
* Routing Index Register (RT_IDX) bit definitions.
*/
/* Nic Queue format - type 2 bits */
/* Hierarchy for the NIC Queue Mask */
enum {
RT_IDX_ALL_ERR_SLOT = 0,
RT_IDX_MAC_ERR_SLOT = 0,
};
enum {
CAM_OUT_ROUTE_FC = 0,
};
/* Function Specific Control Register 0x10 */
/* Configuration Register 0x28 */
#define FN0_NET 0
/*
* Semaphore Register (SEM) bit definitions.
*/
#define SEM_CLEAR 0
#define SEM_XGMAC0_SHIFT 0
/* System Register 0x08 */
/* Interrupt Status Register-1 0x3C */
/* Processor Address Register 0x00 */
/* Semaphor Register 0x64 */
/* XGMAC Address Register 0x78 */
/* XGMAC Register Set */
/* MAC Protocol Address Index Register Set 0xA8 */
/* NIC Receive Configuration Register 0xD4 */
/*
* 10G MAC Address Register (XGMAC_ADDR) bit definitions.
*/
/* Routing Index Register 0xE4 */
/* Routing Data Register 0xE8 */
enum {
};
/*
* General definitions...
*/
/*
* Below are a number compiler switches for controlling driver behavior.
* Some are not supported under certain conditions and are notated as such.
*/
/* MTU & Frame Size stuff */
/ VM_PAGE_SIZE) + 1) + \
(((NUM_LARGE_BUFFERS * sizeof (uint64_t)) \
/ VM_PAGE_SIZE) + 1))
/* coalescing */
/* coalescing */
/* coalescing */
/* coalescing */
/*
* Large & Small Buffers for Receives
*/
struct lrg_buf_q_entry {
};
struct bufq_addr_element {
};
#define QL_NO_RESET 0
/* Link must be in one of these states */
enum link_state_t {
};
/* qlge->flags definitions. */
/*
* ISP PCI Configuration Register Set structure definitions.
*/
typedef volatile struct
{
} pci_cfg_t;
/*
*
* Schultz Control Registers Index
*
*/
/* Interrupt Enable Register 0x34 */
(ONE_INTR_MASK | ENABLE_INTR))
(0x40000000u | GLOBAL_ENABLE_INTR)); \
}
REG_INTERRUPT_ENABLE, (0x40000000u)); \
}
/*
* Mailbox Registers
*/
/*
* Control Register Set definitions.
*/
typedef volatile struct
{
} dev_reg_t;
typedef volatile struct
{
/*
* DMA registers read only
*/
typedef volatile struct
{
#ifdef QL_DEBUG
typedef struct crash_record {
#endif
/*
* I/O register access macros
* #if QL_DEBUG & 1
*/
/*
* QLGE-specific ioctls ...
*/
/*
* Definition of ioctls commands
*/
/* Solaris IOCTL can copy in&out up to 1024 bytes each time */
typedef struct ioctl_header_info {
struct ql_pci_reg {
};
struct ql_device_reg {
};
struct ql_flash_io_info {
};
struct qlnic_mpi_version_info {
};
struct qlnic_link_status_info {
};
struct qlnic_prop_info {
};
typedef struct ql_adapter_info {
typedef struct ql_dump_header {
typedef struct ql_dump_image_header {
/* utility request */
typedef struct ql_dump_footer {
/*
* Solaris qlnic exit status.
*/
/* flash region for testing */
/* mailbox */
/*
* ISP mailbox commands from Host
*/
enum IDC_REQ_DEST_FUNC {
};
/*
* ISP mailbox command complete status codes
*/
/* Async Event Status */
enum {
};
typedef struct firmware_version_info {
typedef struct phy_firmware_version_info {
typedef struct port_cfg_info {
enum {
};
/* Mailbox command parameter structure definition. */
typedef struct mbx_cmd {
} mbx_cmd_t;
/* Returned Mailbox registers. */
typedef struct mbx_data {
} mbx_data_t;
/* 64 probes, 8 bytes per probe + 4 bytes to list the probe ID */
(4096 * 1) + (4 * 2) + (8 * 2) + \
(16 * 1) + (4 * 1) + (4 * 4) + \
(4 * 1))
/* Save both the address and data register */
typedef struct mpi_coredump_global_header {
typedef struct mpi_coredump_segment_header {
typedef struct ql_mpi_coredump {
/* one interrupt state for each CQ */
/* Force byte packing for the following structures */
#pragma pack(1)
/*
* Work Queue (Request Queue) Initialization Control Block (WQICB)
*/
struct wqicb_t {
};
/*
* Completion Queue (Response Queue) Initialization Control Block (CQICB)
*/
struct cqicb_t {
/* producer index host shadow */
};
struct ricb {
};
/*
* Host Command IOCB Formats
*/
/*
* The following constants define control bits for buffer
* length fields for all IOCB's.
*/
struct oal_entry {
};
/* 32 words, 128 bytes */
struct ob_mac_iocb_req {
};
/* 16 words, 64 bytes */
struct ob_mac_iocb_rsp {
};
struct ib_mac_iocb_rsp {
};
/* 16 words, 64 bytes */
struct ib_sys_event_iocb_rsp {
};
/*
* Status Register (#define STATUS) bit definitions.
*/
/*
* Generic Response Queue IOCB Format which abstracts the difference between
* IB_MAC, OB_MAC IOCBs
*/
struct net_rsp_iocb {
};
/* Restore original packing rules */
#pragma pack()
/* flash */
/* Little endian machine correction defines. */
#ifdef _LITTLE_ENDIAN
#define LITTLE_ENDIAN_16(x)
#define LITTLE_ENDIAN_24(x)
#define LITTLE_ENDIAN_32(x)
#define LITTLE_ENDIAN_64(x)
#endif /* _LITTLE_ENDIAN */
/* Big endian machine correction defines. */
#ifdef _BIG_ENDIAN
#define BIG_ENDIAN_16(x)
#define BIG_ENDIAN_24(x)
#define BIG_ENDIAN_32(x)
#define BIG_ENDIAN_64(x)
#endif /* _BIG_ENDIAN */
/* Flash Address Register 0x88 */
/*
* Flash definitions.
*/
typedef struct ql_flash_info {
/*
* Flash Description Table
*/
typedef struct flash_desc {
} flash_desc_t;
/* flash manufacturer id's */
/* flash id defines */
/* flash type defines */
typedef struct {
} pci_header_t;
typedef struct {
} pci_data_t;
#define PCI_CODE_X86PC 0
/* Flash Layout Table Data Structure(FLTDS) */
typedef struct ql_fltds {
} ql_fltds_t;
/* Image Layout Table Data Structure(ILTDS) */
typedef struct ql_iltds_header {
typedef struct ql_iltds_img_entry {
typedef struct ql_iltds_time_stamp {
typedef struct ql_iltds_description_header {
/* flash layout table definition */
/* header */
typedef struct ql_flt_header {
/* table entry */
typedef struct ql_flt_entry {
/* flt table */
typedef struct ql_flt {
} ql_flt_t;
/* Nic Configuration Table */
enum {
};
typedef struct ql_nic_config {
#ifdef __cplusplus
}
#endif
#endif /* _QLGE_HW_H */