a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If applicable, add the following below this CDDL HEADER, with the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * fields enclosed by brackets "[]" replaced with your own identifying
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Copyright (c) 2002-2006 Neterion, Inc.
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Use is subject to license terms.
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* General Control-Status Registers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* XGXS must be removed from reset only once. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* The SW_RESET register must read this value after a successful reset. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* PCI-X Controller registers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* PIC Control registers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Automated statistics collection */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* General Configuration */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48)
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* TxDMA registers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* TxDMA arbiter */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Tx FIFO controller */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Tx Protocol assist */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Recent add, used only debug purposes. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* RxDMA Registers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* DMA arbiter */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Per-ring controller regs */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Receive traffic interrupts */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4))))
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Media Access Controller Register */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 rmac_addr_cfg;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* rx traffic steering */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* memory controller registers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* MC configuration */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* XGXS control registers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Using this strcture to calculate offsets */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_HAL_REGS_H */