/illumos-gate/usr/src/lib/librstp/common/ |
H A D | vector.h | 36 typedef unsigned short PORT_ID; typedef 42 PORT_ID design_port; 43 PORT_ID bridge_port; 51 IN PORT_ID design_port, 52 IN PORT_ID bridge_port);
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H A D | stpm.h | 64 PORT_ID rootPortId; /* 17.17.5 */ 118 STP_stpm_get_port_name_by_id (STPM_T* this, PORT_ID port_id);
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H A D | vector.c | 52 IN PORT_ID design_port, 53 IN PORT_ID bridge_port)
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H A D | port.h | 103 PORT_ID port_id; /* 17.18.16 */
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H A D | stpm.c | 344 STP_stpm_get_port_name_by_id (STPM_T* this, PORT_ID port_id)
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H A D | rolesel.c | 198 PORT_ID old_root_port; /* for tracing of root port changing */
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
H A D | lm_power.c | 80 reg_len = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_LEN_IDX(0,0) : LM_NIG_ACPI_PAT_LEN_IDX(1,0) ; 81 reg_crc = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_CRC_IDX(0,0) : LM_NIG_ACPI_PAT_CRC_IDX(1,0) ; 84 reg_len = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_LEN_IDX(0,1) : LM_NIG_ACPI_PAT_LEN_IDX(1,1) ; 85 reg_crc = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_CRC_IDX(0,1) : LM_NIG_ACPI_PAT_CRC_IDX(1,1) ; 88 reg_len = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_LEN_IDX(0,2) : LM_NIG_ACPI_PAT_LEN_IDX(1,2) ; 89 reg_crc = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_CRC_IDX(0,2) : LM_NIG_ACPI_PAT_CRC_IDX(1,2) ; 92 reg_len = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_LEN_IDX(0,3) : LM_NIG_ACPI_PAT_LEN_IDX(1,3) ; 93 reg_crc = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_CRC_IDX(0,3) : LM_NIG_ACPI_PAT_CRC_IDX(1,3) ; 96 reg_len = (0 == PORT_ID(pdev)) ? LM_NIG_ACPI_PAT_LEN_IDX(0,4) : LM_NIG_ACPI_PAT_LEN_IDX(1,4) ; 97 reg_crc = (0 == PORT_ID(pde [all...] |
H A D | lm_hw_init_reset.c | 53 REG_WR(pdev,(PORT_ID(pdev) ? PXP2_REG_PSWRQ_##blk##1_L2P: PXP2_REG_PSWRQ_##blk##0_L2P),((last)<<10 | (first))); \ 106 ecore_init_block(_pdev, BLOCK_##_block, PHASE_PORT0 + PORT_ID(_pdev)) 304 pdev->flr_stats.tm_vnic_usage_counter = REG_WAIT_VERIFY_VAL(pdev, TM_REG_LIN0_VNIC_UC + 4*PORT_ID(pdev),0, wait_ms); 306 pdev->flr_stats.tm_vnic_usage_counter, DEFAULT_WAIT_INTERVAL_MICSEC, PORT_ID(pdev)); 308 pdev->flr_stats.tm_num_scans_usage_counter = REG_WAIT_VERIFY_VAL(pdev, TM_REG_LIN0_NUM_SCANS + 4*PORT_ID(pdev),0, wait_ms); 310 pdev->flr_stats.tm_num_scans_usage_counter, DEFAULT_WAIT_INTERVAL_MICSEC, PORT_ID(pdev)); 1106 const u32_t nig_mem_enable_base_offset = (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : NIG_REG_LLH0_FUNC_MEM_ENABLE); 1107 const u32_t nig_mem2_enable_base_offset = (PORT_ID(pdev) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE : NIG_REG_P0_LLH_FUNC_MEM2_ENABLE); 1118 REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_EN : NIG_REG_LLH0_FUNC_EN), 0); 1291 const u8_t port = PORT_ID(pde [all...] |
H A D | lm_sb.c | 570 REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_L + 8*PORT_ID(pdev), host_sb_addr->as_u32.low); 571 REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_H + 8*PORT_ID(pdev), host_sb_addr->as_u32.high); 665 u8_t port = PORT_ID(pdev); 679 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0) + group_idx*16); 681 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0) + group_idx*16); 683 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0) + group_idx*16); 685 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0) + group_idx*16); 689 REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0) + group_idx*4); 704 PORT_ID(pdev) ? MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 : MISC_REG_AEU_AFTER_INVERT_1_FUNC_0; 706 PORT_ID(pde [all...] |
H A D | lm_hw_attn.c | 709 if (PORT_ID(pdev) == 0) 751 DbgBreakIf(PORT_ID(pdev) != 1); 798 if (PORT_ID(pdev) == 0) 838 DbgBreakIf(PORT_ID(pdev) != 1); 897 lm_hw_lock(pdev, HW_LOCK_RESOURCE_PORT0_ATT_MASK + PORT_ID(pdev), TRUE); 898 port_reg_name = PORT_ID(pdev) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : MISC_REG_AEU_MASK_ATTN_FUNC_0; 908 lm_hw_unlock(pdev, HW_LOCK_RESOURCE_PORT0_ATT_MASK + PORT_ID(pdev)); 932 nig_mask = REG_RD(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev)); 933 REG_WR(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev), 0); 954 REG_WR(pdev, HC_REG_COMMAND_REG + PORT_ID(pde [all...] |
H A D | lm_devinfo.c | 188 DbgMessage(pdev, WARN, "lm_get_shmem_info: PORT_ID: %d\n", PORT_ID(pdev)); 192 DbgMessage(pdev, WARN, "lm_get_shmem_info: ETH_PORT_ID: %d\n", PATH_ID(pdev) + 2*PORT_ID(pdev)); 196 DbgMessage(pdev, WARN, "lm_get_shmem_info: ETH_PORT_ID: %d\n", PATH_ID(pdev) + PORT_ID(pdev)); 957 blk_info->simd_addr_womask = HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_SIMD_NOMASK; 963 blk_info->simd_addr_wmask = HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_SIMD_NOMASK; 967 blk_info->simd_addr_wmask = HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_SIMD_MASK; 1207 if (PORT_ID(pdev) == port) 1286 port = PORT_ID(pdev); 1493 LM_MFCFG_READ(pdev, OFFSETOF(mf_cfg_t, port_mf_config[PATH_ID(pdev)][PORT_ID(pde [all...] |
H A D | lm_nvram.c | 57 u8_t port_num = PORT_ID(pdev); /* TBD - E1H: nvram lock � DOES NOT scale to 8 functions! (only 4 clients) 109 u8_t port_num = PORT_ID(pdev);
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H A D | lm_phy.c | 246 u8_t port = PORT_ID(pdev); 320 u8_t port = PORT_ID(pdev); 571 LM_SHMEM_READ(pdev,OFFSETOF(shmem_region_t,dev_info.port_hw_config[PORT_ID(pdev)].default_cfg),&port_default_cfg); 606 LM_SHMEM_READ(pdev,OFFSETOF(shmem_region_t,dev_info.port_hw_config[PORT_ID(pdev)].default_cfg),&default_cfg); 778 const u8_t port_id = PORT_ID(pdev); 900 LM_INTMEM_WRITE16(pdev,USTORM_ETH_PAUSE_ENABLED_OFFSET(PORT_ID(pdev)), pause_ena, BAR_USTRORM_INTMEM); 1448 mm_event_log_generic(pdev, LM_LOG_ID_NO_10G_SUPPORT, PORT_ID(pdev) ); 1876 lm_gpio_write(pdev, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_HIGH, PORT_ID(pdev) ); 1967 lm_gpio_write(pdev, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW, PORT_ID(pdev) ); 1973 elink_ext_phy_hw_reset( pdev, PORT_ID(pde [all...] |
H A D | lm_hw_access.c | 67 const u8_t port_id = PORT_ID(pdev); // TBD: E1H - cmng params are currently per port, may change to be per function 1175 port = PORT_ID(pdev); 1212 val = REG_RD(pdev, HC_REG_INT_MASK + 4*PORT_ID(pdev) ); 1424 reg_offset = (PORT_ID(pdev)? NIG_REG_LLH1_FUNC_MEM: NIG_REG_LLH0_FUNC_MEM) + 8*offset; 1428 reg_offset = (PORT_ID(pdev)? NIG_REG_P1_LLH_FUNC_MEM2: NIG_REG_P0_LLH_FUNC_MEM2) + 8*(offset - MAX_OFFSET_IN_MEM_1); 1443 reg_offset = (PORT_ID(pdev)? NIG_REG_LLH1_FUNC_MEM_ENABLE : NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*offset; 1447 reg_offset = (PORT_ID(pdev)? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE : NIG_REG_P0_LLH_FUNC_MEM2_ENABLE) + 4*(offset - MAX_OFFSET_IN_MEM_1);
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H A D | lm_mcp.c | 593 if( ERR_IF(PORT_ID(pdev) > 1) || ERR_IF(( FUNC_ID(pdev)) >= ARRSIZE(g_lm_loader.path_arr[PATH_ID(pdev)].func_arr)) ) 595 DbgBreakMsg("Invalid PORT_ID/FUNC_ID\n"); 630 else if( LM_LOADER_IS_FIRST_ON_PORT( pdev, PATH_ID(pdev), PORT_ID(pdev) ) ) 646 else if( LM_LOADER_IS_LAST_ON_PORT( pdev, PATH_ID(pdev), PORT_ID(pdev) ) )
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H A D | lm_stats.c | 591 val = REG_RD(pdev, HC_REG_INT_MASK + 4*PORT_ID(pdev) ); 704 emac_base = ( 0 == PORT_ID(pdev) ) ? GRCBASE_EMAC0 : GRCBASE_EMAC1 ; 1050 switch (PORT_ID(pdev)) 1066 DbgMessage(NULL, FATAL, "Invalid Port ID %d\n", PORT_ID(pdev)); 1123 lm_dmae_address_t source = lm_dmae_address((0==PORT_ID(pdev))?NIG_REG_STAT0_BRB_DISCARD : NIG_REG_STAT1_BRB_DISCARD, 1199 const u32_t emac_base = (PORT_ID(pdev)==0) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 1308 const u32_t port = PORT_ID(pdev) ; 1376 const u32_t port = PORT_ID(pdev) ; 1501 cur_query_entry->index = PORT_ID(pdev); 1514 cur_query_entry->index = PORT_ID(pde [all...] |
H A D | lm_dmae.c | 90 return HW_LOCK_RESOURCE_PORT0_DMAE_COPY_CMD + PORT_ID(pdev); 259 opcode |= PORT_ID(pdev) << DMAE_CMD_PORT_SHIFT;
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H A D | lm_dcbx.c | 2791 offset += PORT_ID(pdev) * mib_size; 2863 res_ext_offset += PORT_ID(pdev) * sizeof(lldp_local_mib_ext_t); 3128 offset += PORT_ID(pdev) * sizeof(lldp_params_t); 3176 offset += PORT_ID(pdev) * sizeof(mcp_dcbx_stat); 3621 offset += PORT_ID(pdev) * sizeof(mcp_dcbx_stat); 4461 PORT_ID(pdev) * sizeof(lldp_params_t); 4703 const u8_t port = PORT_ID(pdev); 4766 const u8_t port = PORT_ID(pdev); 4873 const u8_t port = PORT_ID(pdev);
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H A D | lm_resc.c | 91 port = PORT_ID(pdev); 767 rcq_chain->iro_prod_offset = USTORM_RX_PRODS_E1X_OFFSET(PORT_ID(pdev), LM_FW_CLI_ID(pdev, cid)); 2175 DMAE_COPY_PCI_PCI_PORT_0_CMD + PORT_ID(pdev),
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/ |
H A D | bnxe_fw_funcs.c | 53 if (PORT_ID(pdev)) { 62 ECORE_PF_Q_NUM(q_num, PORT_ID(pdev), vnic);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/ |
H A D | lm5710.h | 992 #define PORT_ID(pdev) (PORT_ID_PARAM_FUNC_REL(PFDEV(pdev)->params.pfunc_rel)) //0 or 1 macro 997 for ((func) = PORT_ID(pdev); (func) < E1H_FUNC_MAX; (func)+=2) 1003 ((LM_CHIP_PORT_MODE_NONE == CHIP_PORT_MODE(pdev))? PORT_ID(pdev) : (PATH_ID(pdev)+2*PORT_ID(pdev))) 1010 #define FUNC_MAILBOX_ID(pdev) (FUNC_MAILBOX_ID_PARAM(PORT_ID(pdev) ,VNIC_ID(pdev),CHIP_NUM(pdev), CHIP_PORT_MODE(pdev))) 1015 for ((func) = PORT_ID(pdev); (func) < (CHIP_IS_E1x(pdev) ? E1H_FUNC_MAX : E2_FUNC_MAX); (func)+= (CHIP_IS_E1x(pdev) ? 2 : 1)) 1993 PORT_ID(_pdev) * sizeof(lldp_admin_mib_t)) 4348 #define HW_CID(pdev,x) (x |(PORT_ID(pdev) << 23 | VNIC_ID(pdev) << 17))
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/ |
H A D | lm_vf.c | 339 u8_t port = PORT_ID(pdev); 392 u8_t port = PORT_ID(pdev);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l4/ |
H A D | lm_l4tx.c | 543 LM_INTMEM_WRITE16(pdev, CSTORM_TOE_CQ_PROD_OFFSET(LM_TOE_FW_RSS_ID(pdev,drv_toe_rss_id) , PORT_ID(pdev)),
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H A D | lm_l4sp.c | 654 port = PORT_ID(pdev); 747 port = PORT_ID(pdev); 973 if (PORT_ID(pdev)) { 2679 SET_FLAGS( xtcp_st->flags,(PORT_ID(pdev) << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT)); 6228 LM_INTMEM_WRITE32(pdev, USTORM_TOE_GRQ_CONS_PTR_LO_OFFSET(LM_TOE_FW_RSS_ID(pdev,idx), PORT_ID(pdev)), 0, BAR_USTRORM_INTMEM); 6229 LM_INTMEM_WRITE32(pdev, USTORM_TOE_GRQ_CONS_PTR_HI_OFFSET(LM_TOE_FW_RSS_ID(pdev,idx), PORT_ID(pdev)), 0, BAR_USTRORM_INTMEM); 6381 LM_INTMEM_WRITE16(pdev, USTORM_TOE_GRQ_PROD_OFFSET(LM_TOE_FW_RSS_ID(pdev,i), PORT_ID(pdev)),
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/illumos-gate/usr/src/uts/common/io/bnxe/ |
H A D | bnxe_mm.c | 1493 (PATH_ID(pdev) + (2 * PORT_ID(pdev))) : \ 1494 (PATH_ID(pdev) + PORT_ID(pdev))
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