Searched refs:pVCpu (Results 101 - 125 of 149) sorted by relevance

123456

/vbox/include/VBox/vmm/
H A Dpdmapi.h43 VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt);
50 VMMDECL(int) PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base);
51 VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base);
52 VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR);
53 VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending, uint8_t *pu8PendingIrq);
69 VMMR3_INT_DECL(void) PDMR3ResetCpu(PVMCPU pVCpu); variable
H A Dpdmcritsect.h56 VMM_INT_DECL(void) PDMCritSectBothFF(PVMCPU pVCpu); variable
75 VMMDECL(bool) PDMCritSectIsOwnerEx(PCPDMCRITSECT pCritSect, PVMCPU pVCpu);
H A Dcsam.h91 VMMR3_INT_DECL(int) CSAMR3DoPendingAction(PVM pVM, PVMCPU pVCpu);
H A Dhm_vmx.h59 * @param pVCpu Pointer to the VMCPU.
62 #define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
67 * @param pVCpu Pointer to the VMCPU.
70 #define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
76 * @param pVCpu Pointer to the VMCPU.
79 #define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
84 * @param pVCpu Pointe
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H A Duvm.h44 PVMCPU pVCpu; member in struct:UVMCPU
H A Ddbgf.h49 VMMRZ_INT_DECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping);
50 VMMRZ_INT_DECL(int) DBGFRZTrap03Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
296 VMMR3_INT_DECL(int) DBGFR3PrgStep(PVMCPU pVCpu); variable
422 VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu); variable
423 VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue);
912 VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput);
913 VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix);
920 # define DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix) \
923 DBGFR3DisasInstrCurrentLogInternal(pVCpu, pszPrefix); \
926 # define DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefi
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/vbox/src/VBox/VMM/VMMR3/
H A DGIMKvm.cpp328 PVMCPU pVCpu = &pVM->aCpus[i]; local
329 PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
343 Assert(!TMCpuTickIsTicking(pVCpu));
344 rc = gimR3KvmEnableSystemTime(pVM, pVCpu, pKvmCpu, fSystemTimeFlags);
366 * @param pVCpu Pointer to the VMCPU.
374 VMMR3_INT_DECL(int) gimR3KvmEnableSystemTime(PVM pVM, PVMCPU pVCpu, PGIMKVMCPU pKvmCpu, uint8_t fFlags) argument
414 "fFlags=%#x uTsc=%#RX64 uVirtNanoTS=%#RX64\n", pVCpu->idCpu, pKvmCpu->GCPhysSystemTime, SystemTime.u32TscScale,
H A DTM.cpp184 static DECLCALLBACK(VBOXSTRICTRC) tmR3CpuTickParavirtDisable(PVM pVM, PVMCPU pVCpu, void *pvData);
1216 PVMCPU pVCpu = &pVM->aCpus[i]; local
1217 Assert(!pVCpu->tm.s.fTSCTicking);
1244 PVMCPU pVCpu = &pVM->aCpus[i]; local
1245 SSMR3PutU64(pSSM, TMCpuTickGet(pVCpu));
1268 PVMCPU pVCpu = &pVM->aCpus[i]; local
1269 Assert(!pVCpu->tm.s.fTSCTicking);
1335 PVMCPU pVCpu = &pVM->aCpus[i]; local
1337 pVCpu->tm.s.fTSCTicking = false;
1338 SSMR3GetU64(pSSM, &pVCpu
2477 TMR3VirtualSyncFF(PVM pVM, PVMCPU pVCpu) argument
2739 TMR3NotifySuspend(PVM pVM, PVMCPU pVCpu) argument
2787 TMR3NotifyResume(PVM pVM, PVMCPU pVCpu) argument
2850 PVMCPU pVCpu = VMMGetCpu(pVM); local
2934 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
3042 PVMCPU pVCpu = &pVM->aCpus[iCpu]; local
3113 PVMCPU pVCpu = &pVM->aCpus[i]; local
3167 PVMCPU pVCpu = &pVM->aCpus[i]; local
3350 PVMCPU pVCpu = &pVM->aCpus[i]; local
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H A DPGMMap.cpp211 PVMCPU pVCpu = &pVM->aCpus[i]; local
212 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
270 PVMCPU pVCpu = &pVM->aCpus[i]; local
271 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526 PVMCPU pVCpu = &pVM->aCpus[0]; local
532 PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
595 PVMCPU pVCpu local
951 PVMCPU pVCpu = VMMGetCpu(pVM); local
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H A DVM.cpp637 pUVM->aCpus[i].pVCpu = &pVM->aCpus[i];
742 pUVM->aCpus[i].pVCpu = NULL;
748 /* Poke the other EMTs since they may have stale pVM and pVCpu references
1271 * @param pVCpu Pointer to the VMCPU of the EMT.
1274 static DECLCALLBACK(VBOXSTRICTRC) vmR3PowerOn(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
1276 LogFlow(("vmR3PowerOn: pVM=%p pVCpu=%p/#%u\n", pVM, pVCpu, pVCpu->idCpu));
1283 if (pVCpu->idCpu == pVM->cCpus - 1)
1298 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTE
1365 vmR3Suspend(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
1464 vmR3Resume(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
1565 vmR3LiveDoSuspend(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
1665 vmR3LiveDoStep1Cleanup(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
2256 vmR3PowerOff(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
2477 PVMCPU pVCpu = VMMGetCpu(pVM); local
2747 vmR3Reset(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
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H A DPDM.cpp824 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
825 SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC));
826 SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC));
827 SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI));
828 SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI));
854 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
856 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC) ? " VMCPU_FF_INTERRUPT_APIC" : "",
857 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC) ? " VMCPU_FF_INTERRUPT_PIC" : ""));
872 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
873 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_API
917 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
1460 PDMR3ResetCpu(PVMCPU pVCpu) argument
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H A DPGMHandler.cpp405 PVMCPU pVCpu = VMMGetCpu(pVM); local
407 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL | PGM_SYNC_CLEAR_PGM_POOL;
408 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
485 PVMCPU pVCpu = VMMGetCpu(pVM); local
487 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL | PGM_SYNC_CLEAR_PGM_POOL;
488 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
H A DPGMPool.cpp538 PVMCPU pVCpu = VMMGetCpu(pVM); local
555 Log(("CPU%d: pgmR3PoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhys), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
562 /* @todo this code doesn't make any sense. remove the if (!pVCpu) block */
563 if (!pVCpu) /** @todo This shouldn't happen any longer, all access handlers will be called on an EMT. All ring-3 handlers, except MMIO, already own the PGM lock. @bugref{3170} */
578 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhys, pvPhys, 0 /* unknown write size */);
585 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhys, pvPhys, 0 /* unknown write size */);
598 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhys, pvPhys, 0 /* unknown write size */);
620 * @param pVCpu The VMCPU for the EMT we're being called on. Unused.
625 DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl) argument
629 NOREF(pVCpu);
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H A DPGMPhys.cpp942 * @param pVCpu The VMCPU for the EMT we're being called on. Unused.
945 static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysChangeMemBalloonRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
961 pgmR3PoolClearAllRendezvous(pVM, pVCpu, NULL);
1139 * @param pVCpu The VMCPU for the EMT we're being called on. Unused.
1142 static DECLCALLBACK(VBOXSTRICTRC) pgmR3PhysWriteProtectRAMRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
1145 NOREF(pvUser); NOREF(pVCpu);
2261 PVMCPU pVCpu = VMMGetCpu(pVM); local
2262 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
2263 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2441 PVMCPU pVCpu local
2876 PVMCPU pVCpu = VMMGetCpu(pVM); local
2991 PVMCPU pVCpu = VMMGetCpu(pVM); local
3857 PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable) argument
4004 pgmR3PhysUnmapChunkRendezvous(PVM pVM, PVMCPU pVCpu, void *pvUser) argument
4184 PVMCPU pVCpu = VMMGetCpu(pVM); local
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H A DPGMSavedState.cpp3078 PVMCPU pVCpu = &pVM->aCpus[i]; local
3079 pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
3080 pgmR3RefreshShadowModeAfterA20Change(pVCpu);
3221 PVMCPU pVCpu = &pVM->aCpus[i]; local
3222 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3223 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3224 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3244 PVMCPU pVCpu = &pVM->aCpus[i]; local
3246 rc = PGMR3ChangeMode(pVM, pVCpu, pVCp
3314 PVMCPU pVCpu = &pVM->aCpus[0]; local
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/vbox/src/VBox/VMM/VMMAll/
H A DPGMAllPool.cpp170 * @param pVCpu Pointer to the VMCPU.
178 void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, argument
184 NOREF(pVCpu);
274 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
300 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
378 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
379 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
408 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
409 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
427 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR
741 pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault) argument
825 pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault) argument
922 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM)); local
964 pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused) argument
1066 PVMCPU pVCpu = VMMGetCpu(pVM); local
1658 PVMCPU pVCpu = VMMGetCpu(pVM); local
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H A DIEMAll.cpp769 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); local
772 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
773 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
774 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->es));
775 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ds));
776 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->fs));
777 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->gs));
778 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ldtr));
779 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->tr));
783 CPUMGuestLazyLoadHiddenCsAndSs(pVCpu);
830 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); local
3917 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); local
4323 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); local
9550 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); local
9753 PVMCPU pVCpu = VMMGetCpu(pVM); local
9773 PVMCPU pVCpu = VMMGetCpu(pVM); local
9797 PVMCPU pVCpu = VMMGetCpu(pVM); local
9816 PVMCPU pVCpu = VMMGetCpu(pVM); local
9904 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); local
10090 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); local
10471 iemLogCurInstr(PVMCPU pVCpu, PCPUMCTX pCtx, bool fSameCtx) argument
10597 iemExecOneInner(PVMCPU pVCpu, PIEMCPU pIemCpu, bool fExecuteInhibit) argument
10659 iemRCRawMaybeReenter(PIEMCPU pIemCpu, PVMCPU pVCpu, PCPUMCTX pCtx, VBOXSTRICTRC rcStrict) argument
10674 IEMExecOne(PVMCPU pVCpu) argument
10709 IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten) argument
10731 IEMExecOneWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC, const void *pvOpcodeBytes, size_t cbOpcodeBytes) argument
10761 IEMExecOneBypassEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten) argument
10783 IEMExecOneBypassWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC, const void *pvOpcodeBytes, size_t cbOpcodeBytes) argument
10811 IEMExecLots(PVMCPU pVCpu) argument
10891 IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2, uint8_t cbInstr) argument
10950 IEMInjectTrpmEvent(PVMCPU pVCpu) argument
11047 IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode, bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg) argument
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H A DREMAll.cpp208 * @param pVCpu Pointer to the VMCPU of the calling EMT.
210 VMMDECL(void) REMNotifyHandlerPhysicalFlushIfAlmostFull(PVM pVM, PVMCPU pVCpu) argument
212 Assert(pVM->cCpus == 1); NOREF(pVCpu);
/vbox/src/VBox/VMM/VMMRC/
H A DPDMRCDevice.cpp421 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ local
424 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
426 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
446 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */ local
449 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
451 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
498 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
503 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
507 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
510 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NM
530 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
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H A DPATMRC.cpp153 PVMCPU pVCpu = VMMGetCpu0(pVM); local
288 rc = EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
295 PGMRZDynMapReleaseAutoSet(pVCpu);
518 PVMCPU pVCpu = VMMGetCpu0(pVM); local
519 DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
528 rcStrict = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip,
543 rc = EMInterpretInstructionDisasState(pVCpu, &cpu, pRegFrame, 0 /* not relevant here */,
/vbox/src/VBox/VMM/include/
H A DREMInternal.h253 void remR3DumpLnxSyscall(PVMCPU pVCpu);
254 void remR3DumpOBsdSyscall(PVMCPU pVCpu);
H A DGIMHvInternal.h526 VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu); variable
527 VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
528 VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
529 VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
H A DTMInternal.h762 int tmCpuTickPause(PVMCPU pVCpu);
763 int tmCpuTickPauseLocked(PVM pVM, PVMCPU pVCpu);
764 int tmCpuTickResume(PVM pVM, PVMCPU pVCpu);
765 int tmCpuTickResumeLocked(PVM pVM, PVMCPU pVCpu);
/vbox/src/recompiler/
H A DVBoxREMWrapper.cpp2256 REMR3DECL(int) REMR3Step(PVM pVM, PVMCPU pVCpu) argument
2262 return pfnREMR3Step(pVM, pVCpu);
2286 REMR3DECL(int) REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu) argument
2292 return pfnREMR3EmulateInstruction(pVM, pVCpu);
2296 REMR3DECL(int) REMR3Run(PVM pVM, PVMCPU pVCpu) argument
2302 return pfnREMR3Run(pVM, pVCpu);
2306 REMR3DECL(int) REMR3State(PVM pVM, PVMCPU pVCpu) argument
2312 return pfnREMR3State(pVM, pVCpu);
2316 REMR3DECL(int) REMR3StateBack(PVM pVM, PVMCPU pVCpu) argument
2322 return pfnREMR3StateBack(pVM, pVCpu);
2326 REMR3StateUpdate(PVM pVM, PVMCPU pVCpu) argument
2334 REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable) argument
2350 REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage) argument
2428 REMR3NotifyPendingInterrupt(PVM pVM, PVMCPU pVCpu, uint8_t u8Interrupt) argument
2436 REMR3QueryPendingInterrupt(PVM pVM, PVMCPU pVCpu) argument
2446 REMR3NotifyInterruptSet(PVM pVM, PVMCPU pVCpu) argument
2454 REMR3NotifyInterruptClear(PVM pVM, PVMCPU pVCpu) argument
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/vbox/src/VBox/VMM/VMMR0/
H A DHMR0A.asm1128 ; @cproto DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1136 ; @param pVCpu msc:[rbp+30h]
1155 mov rcx, [xBP + 30h] ; pVCpu
1162 mov r10, [xBP + 30h] ; pVCpu
1209 mov r10, [xBP + 30h] ; pVCpu
1256 ; @cproto DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1264 ; @param pVCpu msc:[rbp+30h]
1283 mov rcx, [xBP + 30h] ; pVCpu
1290 mov r10, [xBP + 30h] ; pVCpu
1337 mov r10, [xBP + 30h] ; pVCpu
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