/** @file
* HM - VMX Structures and Definitions. (VMM)
*/
/*
* Copyright (C) 2006-2014 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
#ifndef ___VBox_vmm_vmx_h
#define ___VBox_vmm_vmx_h
/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
when targeting AMD64. */
# include <intrin.h>
/* We always want them as intrinsics, no functions. */
# pragma intrinsic(__vmx_vmclear)
# pragma intrinsic(__vmx_vmptrld)
# pragma intrinsic(__vmx_vmread)
# pragma intrinsic(__vmx_vmwrite)
#else
# define VMX_USE_MSC_INTRINSICS 0
#endif
/** @defgroup grp_vmx vmx Types and Definitions
* @ingroup grp_hm
* @{
*/
/** @def HMVMXCPU_GST_SET_UPDATED
* Sets a guest-state-updated flag.
*
* @param pVCpu Pointer to the VMCPU.
* @param fFlag The flag to set.
*/
#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
/** @def HMVMXCPU_GST_IS_SET
* Checks if all the flags in the specified guest-state-updated set is pending.
*
* @param pVCpu Pointer to the VMCPU.
* @param fFlag The flag to check.
*/
#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
/** @def HMVMXCPU_GST_IS_UPDATED
* Checks if one or more of the flags in the specified guest-state-updated set
* is updated.
*
* @param pVCpu Pointer to the VMCPU.
* @param fFlags The flags to check for.
*/
#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
/** @def HMVMXCPU_GST_RESET_TO
* Resets the guest-state-updated flags to the specified value.
*
* @param pVCpu Pointer to the VMCPU.
* @param fFlags The new value.
*/
#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
/** @def HMVMXCPU_GST_VALUE
* Returns the current guest-state-updated flags value.
*
* @param pVCpu Pointer to the VMCPU.
*/
/** @name Host-state restoration flags.
* @note If you change these values don't forget to update the assembly
* defines as well!
* @{
*/
/** @} */
/**
* Host-state restoration structure.
* This holds host-state fields that require manual restoration.
* Assembly version found in hm_vmx.mac (should be automatically verified).
*/
typedef struct VMXRESTOREHOST
{
/** Pointer to VMXRESTOREHOST. */
/** @name Host-state MSR lazy-restoration flags.
* @{
*/
/** The host MSRs have been saved. */
/** The guest MSRs are loaded and in effect. */
/** @} */
/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
* UFC = Unsupported Feature Combination.
* @{
*/
/** Unsupported pin-based VM-execution controls combo. */
#define VMX_UFC_CTRL_PIN_EXEC 0
/** Unsupported processor-based VM-execution controls combo. */
/** Unsupported pin-based VM-execution controls combo. */
/** Unsupported VM-entry controls combo. */
/** Unsupported VM-exit controls combo. */
* for storing host MSRs. */
* for storing guest MSRs. */
/** Invalid VMCS size. */
/** Unsupported secondary processor-based VM-execution controls combo. */
/** Invalid unrestricted-guest execution controls combo. */
/** @} */
/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
* IGS = Invalid Guest State.
* @{
*/
/** An error occurred while checking invalid-guest-state. */
#define VMX_IGS_ERROR 0
/** The invalid guest-state checks did not find any reason why. */
/** CR0 fixed1 bits invalid. */
/** CR0 fixed0 bits invalid. */
/** CR4 fixed1 bits invalid. */
/** CR4 fixed0 bits invalid. */
/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
/** CR0.PG not set for long-mode when not using unrestricted guest. */
/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
/** CR4.PCIDE set for 32-bit guest. */
/** VMCS' DR7 reserved bits not set to 0. */
/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
/** VMCS' EFER MSR reserved bits not set to 0. */
/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
* without unrestricted guest. */
/** CS.Attr.P bit invalid. */
/** CS.Attr reserved bits not set to 0. */
/** CS.Attr.G bit invalid. */
/** CS is unusable. */
/** CS and SS DPL unequal. */
/** CS and SS DPL mismatch. */
/** CS Attr.Type invalid. */
/** CS and SS RPL unequal. */
/** SS.Attr.DPL and SS RPL unequal. */
/** SS.Attr.DPL invalid for segment type. */
/** SS.Attr.Type invalid. */
/** SS.Attr.P bit invalid. */
/** SS.Attr reserved bits not set to 0. */
/** SS.Attr.G bit invalid. */
/** DS.Attr.A bit invalid. */
/** DS.Attr.P bit invalid. */
/** DS.Attr.DPL and DS RPL unequal. */
/** DS.Attr reserved bits not set to 0. */
/** DS.Attr.G bit invalid. */
/** DS.Attr.Type invalid. */
/** ES.Attr.A bit invalid. */
/** ES.Attr.P bit invalid. */
/** ES.Attr.DPL and DS RPL unequal. */
/** ES.Attr reserved bits not set to 0. */
/** ES.Attr.G bit invalid. */
/** ES.Attr.Type invalid. */
/** FS.Attr.A bit invalid. */
/** FS.Attr.P bit invalid. */
/** FS.Attr.DPL and DS RPL unequal. */
/** FS.Attr reserved bits not set to 0. */
/** FS.Attr.G bit invalid. */
/** FS.Attr.Type invalid. */
/** GS.Attr.A bit invalid. */
/** GS.Attr.P bit invalid. */
/** GS.Attr.DPL and DS RPL unequal. */
/** GS.Attr reserved bits not set to 0. */
/** GS.Attr.G bit invalid. */
/** GS.Attr.Type invalid. */
/** V86 mode CS.Base invalid. */
/** V86 mode CS.Limit invalid. */
/** V86 mode CS.Attr invalid. */
/** V86 mode SS.Base invalid. */
/** V86 mode SS.Limit invalid. */
/** V86 mode SS.Attr invalid. */
/** V86 mode DS.Base invalid. */
/** V86 mode DS.Limit invalid. */
/** V86 mode DS.Attr invalid. */
/** V86 mode ES.Base invalid. */
/** V86 mode ES.Limit invalid. */
/** V86 mode ES.Attr invalid. */
/** V86 mode FS.Base invalid. */
/** V86 mode FS.Limit invalid. */
/** V86 mode FS.Attr invalid. */
/** V86 mode GS.Base invalid. */
/** V86 mode GS.Limit invalid. */
/** V86 mode GS.Attr invalid. */
/** Longmode CS.Base invalid. */
/** Longmode SS.Base invalid. */
/** Longmode DS.Base invalid. */
/** Longmode ES.Base invalid. */
/** SYSENTER ESP is not canonical. */
/** SYSENTER EIP is not canonical. */
/** PAT MSR invalid. */
/** PAT MSR reserved bits not set to 0. */
/** GDTR.Base is not canonical. */
/** IDTR.Base is not canonical. */
/** GDTR.Limit invalid. */
/** IDTR.Limit invalid. */
/** Longmode RIP is invalid. */
/** RFLAGS reserved bits not set to 0. */
/** RFLAGS RA1 reserved bits not set to 1. */
/** RFLAGS.VM (V86 mode) invalid. */
/** RFLAGS.IF invalid. */
/** Activity state invalid. */
/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
/** Activity state SIPI WAIT invalid. */
/** Interruptibility state reserved bits not set to 0. */
/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
/** Interruptibility state block-by-STI invalid for EFLAGS. */
/** Interruptibility state invalid while trying to deliver external
* interrupt. */
/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
* NMI. */
/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
* an NMI. */
/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
* active. */
/** Pending debug exceptions reserved bits not set to 0. */
/** Longmode pending debug exceptions reserved bits not set to 0. */
/** Pending debug exceptions.BS bit is not set when it should be. */
/** Pending debug exceptions.BS bit is not clear when it should be. */
/** VMCS link pointer reserved bits not set to 0. */
/** TR cannot index into LDT, TI bit MBZ. */
/** LDTR cannot index into LDT. TI bit MBZ. */
/** TR.Base is not canonical. */
/** FS.Base is not canonical. */
/** GS.Base is not canonical. */
/** LDTR.Base is not canonical. */
/** TR is unusable. */
/** TR.Attr.S bit invalid. */
/** TR is not present. */
/** TR.Attr reserved bits not set to 0. */
/** TR.Attr.G bit invalid. */
/** Longmode TR.Attr.Type invalid. */
/** TR.Attr.Type invalid. */
/** CS.Attr.S invalid. */
/** CS.Attr.DPL invalid. */
/** PAE PDPTE reserved bits not set to 0. */
/** @} */
/** @name VMX VMCS-Read cache indices.
* @{
*/
#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
/** @} */
/** @name VMX EPT paging structures
* @{
*/
/**
*/
/**
* EPT Page Directory Pointer Entry. Bit view.
* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
*/
typedef struct EPTPML4EBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** Reserved (must be 0). */
/** Available for software. */
/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPML4EBITS;
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
/** The page shift to get the PML4 index. */
/** The PML4 index mask (apply to a shifted page address). */
/**
* EPT PML4E.
*/
typedef union EPTPML4E
{
/** Normal view. */
EPTPML4EBITS n;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPML4E;
/** Pointer to a PML4 table entry. */
/** Pointer to a const PML4 table entry. */
/**
* EPT PML4 Table.
*/
typedef struct EPTPML4
{
} EPTPML4;
/** Pointer to an EPT PML4 Table. */
/** Pointer to a const EPT PML4 Table. */
/**
* EPT Page Directory Pointer Entry. Bit view.
*/
typedef struct EPTPDPTEBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** Reserved (must be 0). */
/** Available for software. */
/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPDPTEBITS;
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
/** The page shift to get the PDPT index. */
/** The PDPT index mask (apply to a shifted page address). */
/**
* EPT Page Directory Pointer.
*/
typedef union EPTPDPTE
{
/** Normal view. */
EPTPDPTEBITS n;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPDPTE;
/** Pointer to an EPT Page Directory Pointer Entry. */
/** Pointer to a const EPT Page Directory Pointer Entry. */
/**
* EPT Page Directory Pointer Table.
*/
typedef struct EPTPDPT
{
} EPTPDPT;
/** Pointer to an EPT Page Directory Pointer Table. */
/** Pointer to a const EPT Page Directory Pointer Table. */
/**
* EPT Page Directory Table Entry. Bit view.
*/
typedef struct EPTPDEBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** Reserved (must be 0). */
/** Big page (must be 0 here). */
/** Available for software. */
/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPDEBITS;
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
/** The page shift to get the PD index. */
/** The PD index mask (apply to a shifted page address). */
/**
* EPT 2MB Page Directory Table Entry. Bit view.
*/
typedef struct EPTPDE2MBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** EPT Table Memory Type. MBZ for non-leaf nodes. */
/** Ignore PAT memory type */
/** Big page (must be 1 here). */
/** Available for software. */
/** Reserved (must be 0). */
/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPDE2MBITS;
/** Bits 21-51 - - EPT - Physical Page number of the next level. */
/**
* EPT Page Directory Table Entry.
*/
typedef union EPTPDE
{
/** Normal view. */
EPTPDEBITS n;
/** 2MB view (big). */
EPTPDE2MBITS b;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPDE;
/** Pointer to an EPT Page Directory Table Entry. */
/** Pointer to a const EPT Page Directory Table Entry. */
/**
* EPT Page Directory Table.
*/
typedef struct EPTPD
{
EPTPDE a[EPT_PG_ENTRIES];
} EPTPD;
/** Pointer to an EPT Page Directory Table. */
/** Pointer to a const EPT Page Directory Table. */
/**
* EPT Page Table Entry. Bit view.
*/
typedef struct EPTPTEBITS
{
/** 0 - Present bit.
* @remark This is a convenience "misnomer". The bit actually indicates
* read access and the CPU will consider an entry with any of the
* first three bits set as present. Since all our valid entries
* will have this bit set, it can be used as a present indicator
* and allow some code sharing. */
/** 1 - Writable bit. */
/** 2 - Executable bit. */
/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
/** 6 - Ignore PAT memory type */
/** 11:7 - Available for software. */
/** 51:12 - Physical address of page. Restricted by maximum physical
* address width of the cpu. */
/** 63:52 - Available for software. */
} EPTPTEBITS;
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
/** The page shift to get the EPT PTE index. */
/** The EPT PT index mask (apply to a shifted page address). */
/**
* EPT Page Table Entry.
*/
typedef union EPTPTE
{
/** Normal view. */
EPTPTEBITS n;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPTE;
/** Pointer to an EPT Page Directory Table Entry. */
/** Pointer to a const EPT Page Directory Table Entry. */
/**
* EPT Page Table.
*/
typedef struct EPTPT
{
EPTPTE a[EPT_PG_ENTRIES];
} EPTPT;
/** Pointer to an extended page table. */
/** Pointer to a const extended table. */
/** @} */
/** VMX VPID flush types.
* Warning!! Valid enum members are in accordance to the VT-x spec.
*/
typedef enum
{
/** Invalidate a specific page. */
/** Invalidate one context (specific VPID). */
/** Invalidate all contexts (all VPIDs). */
/** Invalidate a single VPID context retaining global mappings. */
/** Unsupported by VirtualBox. */
/** Unsupported by CPU. */
} VMXFLUSHVPID;
/** VMX EPT flush types.
* @note Warning!! Valid enums values below are in accordance to the VT-x spec.
*/
typedef enum
{
/** Invalidate one context (specific EPT). */
/* Invalidate all contexts (all EPTs) */
/** Unsupported by VirtualBox. */
/** Unsupported by CPU. */
} VMXFLUSHEPT;
* In accordance to VT-x spec.
*/
typedef struct
{
/** The MSR Id. */
/** Reserved (MBZ). */
/** The MSR value. */
} VMXAUTOMSR;
/**
* VMX-capability qword
*/
typedef union
{
struct
{
/** Bits set here -must- be set in the correpsonding VM-execution controls. */
/** Bits cleared here -must- be cleared in the corresponding VM-execution
* controls. */
} n;
uint64_t u;
/**
* VMX MSRs.
*/
typedef struct VMXMSRS
{
} VMXMSRS;
/** Pointer to a VMXMSRS struct. */
/** @name VMX EFLAGS reserved bits.
* @{
*/
/** And-mask for setting reserved bits to zero */
/** Or-mask for setting reserved bits to 1 */
/** @} */
/** @name VMX Basic Exit Reasons.
* @{
*/
/** -1 Invalid exit code */
/** 0 Exception or non-maskable interrupt (NMI). */
#define VMX_EXIT_XCPT_OR_NMI 0
/** 1 External interrupt. */
/** 2 Triple fault. */
/** 3 INIT signal. */
/** 4 Start-up IPI (SIPI). */
/** 5 I/O system-management interrupt (SMI). */
/** 6 Other SMI. */
/** 7 Interrupt window exiting. */
/** 8 NMI window exiting. */
/** 9 Task switch. */
/** 10 Guest software attempted to execute CPUID. */
/** 11 Guest software attempted to execute GETSEC. */
/** 12 Guest software attempted to execute HLT. */
/** 13 Guest software attempted to execute INVD. */
/** 14 Guest software attempted to execute INVLPG. */
/** 15 Guest software attempted to execute RDPMC. */
/** 16 Guest software attempted to execute RDTSC. */
/** 17 Guest software attempted to execute RSM in SMM. */
/** 18 Guest software executed VMCALL. */
/** 19 Guest software executed VMCLEAR. */
/** 20 Guest software executed VMLAUNCH. */
/** 21 Guest software executed VMPTRLD. */
/** 22 Guest software executed VMPTRST. */
/** 23 Guest software executed VMREAD. */
/** 24 Guest software executed VMRESUME. */
/** 25 Guest software executed VMWRITE. */
/** 26 Guest software executed VMXOFF. */
/** 27 Guest software executed VMXON. */
/** 28 Control-register accesses. */
/** 29 Debug-register accesses. */
/** 30 I/O instruction. */
/** 31 RDMSR. Guest software attempted to execute RDMSR. */
/** 32 WRMSR. Guest software attempted to execute WRMSR. */
/** 33 VM-entry failure due to invalid guest state. */
/** 34 VM-entry failure due to MSR loading. */
/** 36 Guest software executed MWAIT. */
/** 37 VM-exit due to monitor trap flag. */
/** 39 Guest software attempted to execute MONITOR. */
/** 40 Guest software attempted to execute PAUSE. */
/** 41 VM-entry failure due to machine-check. */
/** 43 TPR below threshold. Guest software executed MOV to CR8. */
/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
/** 50 INVEPT. Guest software attempted to execute INVEPT. */
/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
/** 53 INVVPID. Guest software attempted to execute INVVPID. */
/** 54 WBINVD. Guest software attempted to execute WBINVD. */
/** 55 XSETBV. Guest software attempted to execute XSETBV. */
/** 57 RDRAND. Guest software attempted to execute RDRAND. */
/** 58 INVPCID. Guest software attempted to execute INVPCID. */
/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
/** 60 ??? */
/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
* enabled. */
/** 62 ??? */
/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
/** The maximum exit value (inclusive). */
/** @} */
/** @name VM Instruction Errors
* @{
*/
/** VMCALL executed in VMX root operation. */
/** VMCLEAR with invalid physical address. */
/** VMCLEAR with VMXON pointer. */
/** VMLAUNCH with non-clear VMCS. */
/** VMRESUME with non-launched VMCS. */
/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
/** VM-entry with invalid control field(s). */
/** VM-entry with invalid host-state field(s). */
/** VMPTRLD with invalid physical address. */
/** VMPTRLD with VMXON pointer. */
/** VMPTRLD with incorrect VMCS revision identifier. */
/** VMWRITE to read-only VMCS component. */
/** VMXON executed in VMX root operation. */
/** VM-entry with invalid executive-VMCS pointer. */
/** VM-entry with non-launched executive VMCS. */
/** VM-entry with executive-VMCS pointer not VMXON pointer. */
/** VMCALL with non-clear VMCS. */
/** VMCALL with invalid VM-exit control fields. */
/** VMCALL with incorrect MSEG revision identifier. */
/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
/** VMCALL with invalid SMM-monitor features. */
/** VM-entry with invalid VM-execution control fields in executive VMCS. */
/** VM-entry with events blocked by MOV SS. */
/** @} */
/** @name VMX MSRs - Basic VMX information.
* @{
*/
/** VMCS revision identifier used by the processor. */
/** Size of the VMCS. */
/** Width of physical address used for the VMCS.
* 0 -> limited to the available amount of physical ram
* 1 -> within the first 4 GB
*/
/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
/** Memory type that must be used for the VMCS. */
/** @} */
/** @name VMX MSRs - Misc VMX info.
* @{
*/
/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
/** Activity states supported by the implementation. */
/** Number of CR3 target values supported by the processor. (0-256) */
/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
/** Whether VMWRITE can be used to write VM-exit information fields. */
/** MSEG revision identifier used by the processor. */
/** @} */
/** @name VMX MSRs - VMCS enumeration field info
* @{
*/
/** Highest field index. */
/** @} */
/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
* @{
*/
/** @} */
/** @name Extended Page Table Pointer (EPTP)
* @{
*/
/** Uncachable EPT paging structure memory type. */
#define VMX_EPT_MEMTYPE_UC 0
/** Write-back EPT paging structure memory type. */
/** Shift value to get the EPT page walk length (bits 5-3) */
/** Mask value to get the EPT page walk length (bits 5-3) */
/** Default EPT page-walk length (1 less than the actual EPT page-walk
* length) */
/** @} */
/** @name VMCS field encoding - 16 bits guest fields
* @{
*/
/** @} */
/** @name VMCS field encoding - 16 bits host fields
* @{
*/
/** @} */
/** @name VMCS field encoding - 64 bits host fields
* @{
*/
/** @} */
/** @name VMCS field encoding - 64 Bits control fields
* @{
*/
/* Optional */
/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
/** Extended page table pointer. */
/** Extended page table pointer lists. */
/** VM-exit guest phyiscal address. */
/** @} */
/** @name VMCS field encoding - 64 Bits guest fields
* @{
*/
/** @} */
/** @name VMCS field encoding - 32 Bits control fields
* @{
*/
/** @} */
/** @name VMX_VMCS_CTRL_PIN_EXEC
* @{
*/
/** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
/** Virtual NMIs. */
/** Activate VMX preemption timer. */
/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
/** @} */
/** @name VMX_VMCS_CTRL_PROC_EXEC
* @{
*/
/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
/** Use timestamp counter offset. */
/** VM-exit when executing the HLT instruction. */
/** VM-exit when executing the INVLPG instruction. */
/** VM-exit when executing the MWAIT instruction. */
/** VM-exit when executing the RDPMC instruction. */
/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** VM-exit on CR8 loads. */
/** VM-exit on CR8 stores. */
/** Use TPR shadow. */
/** VM-exit when virtual NMI blocking is disabled. */
/** VM-exit when executing a MOV DRx instruction. */
/** VM-exit when executing IO instructions. */
/** Use IO bitmaps. */
/** Monitor trap flag. */
/** Use MSR bitmaps. */
/** VM-exit when executing the MONITOR instruction. */
/** VM-exit when executing the PAUSE instruction. */
/** Determines whether the secondary processor based VM-execution controls are used. */
/** @} */
/** @name VMX_VMCS_CTRL_PROC_EXEC2
* @{
*/
/** Virtualize APIC access. */
/** Descriptor table instructions cause VM-exits. */
/** Virtualize x2APIC mode. */
/** VM-exit when executing the WBINVD instruction. */
/** Unrestricted guest execution. */
/** A specified nr of pause loops cause a VM-exit. */
/** VM-exit when executing RDRAND instructions. */
/** Enables INVPCID instructions. */
/** Enables VMFUNC instructions. */
/** Enables VMCS shadowing. */
/** VM-exit when executing RDSEED. */
/** Controls whether EPT-violations may cause \#VE instead of exits. */
/** @} */
/** @name VMX_VMCS_CTRL_ENTRY
* @{
*/
/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
/** In SMM mode after VM-entry. */
/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
/** @} */
/** @name VMX_VMCS_CTRL_EXIT
* @{
*/
/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** Return to long mode after a VM-exit. */
/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
/** @} */
/** @name VMX_VMCS_CTRL_VMFUNC
* @{
*/
/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
/** @} */
/** @name VMCS field encoding - 32 Bits read-only fields
* @{
*/
/** @} */
/** @name VMX_VMCS32_RO_EXIT_REASON
* @{
*/
/** @} */
/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
* @{
*/
/** @} */
/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
* @{
*/
#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
/** @} */
/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
* @{
*/
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
/** @} */
/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
* @{
*/
#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
/** @} */
/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
* @{
*/
#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
/** @} */
/** @name VMCS field encoding - 32 Bits guest state fields
* @{
*/
/** @} */
/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
* @{
*/
/** The logical processor is active. */
/** The logical processor is inactive, because executed a HLT instruction. */
/** The logical processor is inactive, because of a triple fault or other serious error. */
/** The logical processor is inactive, because it's waiting for a startup-IPI */
/** @} */
/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
* @{
*/
/** @} */
/** @name VMCS field encoding - 32 Bits host state fields
* @{
*/
/** @} */
/** @name Natural width control fields
* @{
*/
/** @} */
/** @name Natural width read-only data fields
* @{
*/
/** @} */
/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
* @{
*/
/** 0-2: Debug register number */
/** 3: Reserved; cleared to 0. */
/** 4: Direction of move (0 = write, 1 = read) */
/** 5-7: Reserved; cleared to 0. */
/** 8-11: General purpose register number. */
/** Rest: reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
* @{
*/
/** @} */
/** @name CRx accesses
* @{
*/
/** 0-3: Control register number (0 for CLTS & LMSW) */
/** 4-5: Access type. */
/** 6: LMSW operand type */
/** 7: Reserved; cleared to 0. */
/** 8-11: General purpose register number (0 for CLTS & LMSW). */
/** 12-15: Reserved; cleared to 0. */
/** 16-31: LMSW source data (else 0). */
/* Rest: reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
* @{
*/
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
/** @} */
/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
* @{
*/
/** Task switch caused by a call instruction. */
/** Task switch caused by an iret instruction. */
/** Task switch caused by a jmp instruction. */
/** Task switch caused by an interrupt gate. */
/** @} */
/** @name VMX_EXIT_EPT_VIOLATION
* @{
*/
/** Set if the violation was caused by a data read. */
/** Set if the violation was caused by a data write. */
/** Set if the violation was caused by an insruction fetch. */
/** AND of the present bit of all EPT structures. */
/** AND of the write bit of all EPT structures. */
/** AND of the execute bit of all EPT structures. */
/** Set if the guest linear address field contains the faulting address. */
/** If bit 7 is one: (reserved otherwise)
* 1 - violation due to physical address access.
*/
/** @} */
/** @name VMX_EXIT_PORT_IO
* @{
*/
/** 0-2: IO operation width. */
/** 3: IO operation direction. */
/** 4: String IO operation (INS / OUTS). */
/** 5: Repeated IO operation. */
/** 6: Operand encoding. */
/** 16-31: IO Port (0-0xffff). */
/* Rest reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
* @{
*/
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
/** @} */
/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
* @{
*/
#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
/** @} */
/** @name VMX_EXIT_APIC_ACCESS
* @{
*/
/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
/** 12-15: Access type. */
/* Rest reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE return values
* @{
*/
/** Linear read access. */
#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
/** Linear write access. */
/** Linear instruction fetch access. */
/** Physical access for an instruction fetch or during instruction execution. */
/** @} */
/** @name VMCS field encoding - Natural width guest state fields
* @{
*/
/** @} */
/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
* Bits 4-11, 13 and 15-63 are reserved.
* @{
*/
/** Hardware breakpoint 0 was met. */
/** Hardware breakpoint 1 was met. */
/** Hardware breakpoint 2 was met. */
/** Hardware breakpoint 3 was met. */
/** At least one data or IO breakpoint was hit. */
/** A debug exception would have been triggered by single-step execution mode. */
/** @} */
/** @name VMCS field encoding - Natural width host state fields
* @{
*/
/** @} */
/** @defgroup grp_vmx_asm vmx assembly helpers
* @{
*/
/**
* Restores some host-state fields that need not be done on every VM-exit.
*
* @returns VBox status code.
* @param fRestoreHostFlags Flags of which host registers needs to be
* restored.
* @param pRestoreHost Pointer to the host-restore structure.
*/
/**
* Dispatches an NMI to the host.
*/
DECLASM(int) VMXDispatchHostNmi(void);
/**
* Executes VMXON
*
* @returns VBox status code
* @param pVMXOn Physical address of VMXON structure
*/
#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#else
{
"push %3 \n\t"
"push %2 \n\t"
".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
"ja 2f \n\t"
"je 1f \n\t"
"jmp 2f \n\t"
"1: \n\t"
"2: \n\t"
"add $8, %%esp \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
:"memory"
);
return rc;
return VINF_SUCCESS;
# else
int rc = VINF_SUCCESS;
{
_emit 0xF3
_emit 0x0F
_emit 0xC7
_emit 0x34
}
return rc;
# endif
}
#endif
/**
* Executes VMXOFF
*/
#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
DECLASM(void) VMXDisable(void);
#else
{
".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
);
__vmx_off();
# else
{
_emit 0x0F
_emit 0x01
}
# endif
}
#endif
/**
* Executes VMCLEAR
*
* @returns VBox status code
* @param pVMCS Physical address of VM control structure
*/
#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#else
{
"push %3 \n\t"
"push %2 \n\t"
".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
"jnc 1f \n\t"
"1: \n\t"
"add $8, %%esp \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
:"memory"
);
return rc;
return VINF_SUCCESS;
return VERR_VMX_INVALID_VMCS_PTR;
# else
int rc = VINF_SUCCESS;
{
_emit 0x66
_emit 0x0F
_emit 0xC7
_emit 0x34
}
return rc;
# endif
}
#endif
/**
* Executes VMPTRLD
*
* @returns VBox status code
* @param pVMCS Physical address of VMCS structure
*/
#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#else
{
"push %3 \n\t"
"push %2 \n\t"
".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
"jnc 1f \n\t"
"1: \n\t"
"add $8, %%esp \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
);
return rc;
return VINF_SUCCESS;
return VERR_VMX_INVALID_VMCS_PTR;
# else
int rc = VINF_SUCCESS;
{
_emit 0x0F
_emit 0xC7
_emit 0x34
}
return rc;
# endif
}
#endif
/**
* Executes VMPTRST
*
* @returns VBox status code
* @param pVMCS Address that will receive the current pointer
*/
/**
* Executes VMWRITE
*
* @returns VBox status code
* @retval VINF_SUCCESS
* @retval VERR_VMX_INVALID_VMCS_PTR
* @retval VERR_VMX_INVALID_VMCS_FIELD
*
* @param idxField VMCS index
* @param u32Val 32 bits value
*
* @remarks The values of the two status codes can be ORed together, the result
* will be VERR_VMX_INVALID_VMCS_PTR.
*/
#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#else
{
".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
"ja 2f \n\t"
"je 1f \n\t"
"jmp 2f \n\t"
"1: \n\t"
"2: \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
"a"(idxField),
"d"(u32Val)
);
return rc;
return VINF_SUCCESS;
#else
int rc = VINF_SUCCESS;
{
_emit 0x0F
_emit 0x79
_emit 0x04
}
return rc;
# endif
}
#endif
/**
* Executes VMWRITE
*
* @returns VBox status code
* @retval VINF_SUCCESS
* @retval VERR_VMX_INVALID_VMCS_PTR
* @retval VERR_VMX_INVALID_VMCS_FIELD
*
* @param idxField VMCS index
* @param u64Val 16, 32 or 64 bits value
*
* @remarks The values of the two status codes can be ORed together, the result
* will be VERR_VMX_INVALID_VMCS_PTR.
*/
#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
# else /* VMX_USE_MSC_INTRINSICS */
{
return VINF_SUCCESS;
}
# endif /* VMX_USE_MSC_INTRINSICS */
#else
# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
#endif
#else /* ARCH_BITS == 64 */
#endif
/**
* Invalidate a page using invept
* @returns VBox status code
* @param enmFlush Type of flush
* @param pDescriptor Descriptor
*/
/**
* Invalidate a page using invvpid
* @returns VBox status code
* @param enmFlush Type of flush
* @param pDescriptor Descriptor
*/
/**
* Executes VMREAD
*
* @returns VBox status code
* @retval VINF_SUCCESS
* @retval VERR_VMX_INVALID_VMCS_PTR
* @retval VERR_VMX_INVALID_VMCS_FIELD
*
* @param idxField VMCS index
* @param pData Ptr to store VM field value
*
* @remarks The values of the two status codes can be ORed together, the result
* will be VERR_VMX_INVALID_VMCS_PTR.
*/
#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#else
{
".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
"ja 2f \n\t"
"je 1f \n\t"
"jmp 2f \n\t"
"1: \n\t"
"2: \n\t"
:"=&r"(rc),
"=d"(*pData)
:"a"(idxField),
"d"(0)
);
return rc;
unsigned char rcMsc;
# if ARCH_BITS == 32
# else
# endif
return VINF_SUCCESS;
#else
int rc = VINF_SUCCESS;
{
_emit 0x0F
_emit 0x78
_emit 0x04
}
return rc;
# endif
}
#endif
/**
* Executes VMREAD
*
* @returns VBox status code
* @retval VINF_SUCCESS
* @retval VERR_VMX_INVALID_VMCS_PTR
* @retval VERR_VMX_INVALID_VMCS_FIELD
*
* @param idxField VMCS index
* @param pData Ptr to store VM field value
*
* @remarks The values of the two status codes can be ORed together, the result
* will be VERR_VMX_INVALID_VMCS_PTR.
*/
#else
{
unsigned char rcMsc;
# if ARCH_BITS == 32
# else
# endif
return VINF_SUCCESS;
int rc;
return rc;
# else
# error "Shouldn't be here..."
# endif
}
#endif
/**
* Gets the last instruction error value from the current VMCS
*
* @returns error value
*/
{
#if ARCH_BITS == 64
return (uint32_t)uLastError;
#else /* 32-bit host: */
uint32_t uLastError = 0;
return uLastError;
#endif
}
#ifdef IN_RING0
#endif /* IN_RING0 */
/** @} */
/** @} */
#endif