236b2935f217749893b7034e59da3e3568928acevboxsync/* $Id$ */
236b2935f217749893b7034e59da3e3568928acevboxsync/** @file
236b2935f217749893b7034e59da3e3568928acevboxsync * GIM - Hyper-V, Internal header file.
236b2935f217749893b7034e59da3e3568928acevboxsync */
236b2935f217749893b7034e59da3e3568928acevboxsync
236b2935f217749893b7034e59da3e3568928acevboxsync/*
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsync * Copyright (C) 2014-2015 Oracle Corporation
236b2935f217749893b7034e59da3e3568928acevboxsync *
236b2935f217749893b7034e59da3e3568928acevboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
236b2935f217749893b7034e59da3e3568928acevboxsync * available from http://www.virtualbox.org. This file is free software;
236b2935f217749893b7034e59da3e3568928acevboxsync * you can redistribute it and/or modify it under the terms of the GNU
236b2935f217749893b7034e59da3e3568928acevboxsync * General Public License (GPL) as published by the Free Software
236b2935f217749893b7034e59da3e3568928acevboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
236b2935f217749893b7034e59da3e3568928acevboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
236b2935f217749893b7034e59da3e3568928acevboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
236b2935f217749893b7034e59da3e3568928acevboxsync */
236b2935f217749893b7034e59da3e3568928acevboxsync
236b2935f217749893b7034e59da3e3568928acevboxsync#ifndef ___GIMHvInternal_h
236b2935f217749893b7034e59da3e3568928acevboxsync#define ___GIMHvInternal_h
236b2935f217749893b7034e59da3e3568928acevboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync#include <VBox/vmm/gim.h>
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#include <VBox/vmm/cpum.h>
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
498be3e6aacdd97907a70c49fc956d018db0ac8avboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @name Hyper-V base feature identification.
157093a77f2752732368338110cb50fa6cd7717fvboxsync * Features based on current partition privileges (per-VM).
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * @{
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Virtual processor runtime MSR available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Partition reference counter MSR available. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Basic Synthetic Interrupt Controller MSRs available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_BASIC_SYNTH_IC RT_BIT(2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Synthetic Timer MSRs available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_SYNTH_TIMER_MSRS RT_BIT(3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** APIC access MSRs (EOI, ICR, TPR) available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Hypercall MSRs available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Access to VCPU index MSR available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Virtual system reset MSR available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Statistic pages MSRs available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Paritition reference TSC MSR available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Virtual guest idle state MSR available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Timer frequency MSRs (TSC and APIC) available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Debug MSRs available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @} */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @name Hyper-V partition-creation feature identification.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * Indicates flags specified during partition creation.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * @{
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Create partitions. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Access partition Id. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Access memory pool. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Adjust message buffers. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Post messages. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Signal events. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Create port. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Connect port. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Access statistics. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Debugging.*/
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** CPU management. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** CPU profiler. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Enable expanded stack walking. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @} */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @name Hyper-V power management feature identification.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * @{
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Maximum CPU power state C0. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Maximum CPU power state C1. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Maximum CPU power state C2. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Maximum CPU power state C3. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** HPET is required to enter C3 power state. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @} */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @name Hyper-V miscellaneous feature identification.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * Miscellaneous features available for the current partition.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * @{
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** MWAIT instruction available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest debugging support available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Performance monitor support is available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for physical CPU dynamic partitioning events. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for passing hypercall input parameter block via XMM registers. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for virtual guest idle state. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for hypervisor sleep state. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for querying NUMA distances. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for determining timer frequencies. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for injecting synthetic machine checks. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_INJECT_SYNTH_MC_XCPT RT_BIT(9)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for guest crash MSRs. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Support for debug MSRs. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Npiep1 Available */ /** @todo What the heck is this? */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Disable hypervisor available. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @} */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @name Hyper-V implementation recommendations.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * Recommendations from the hypervisor for the guest for optimal performance.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * @{
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use hypercall for address space switches rather than MOV CR3. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use hypervisor provided MSR for a system reset. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * timely deliver of external interrupts. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use DMA remapping. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use interrupt remapping. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Use X2APIC MSRs rather than MMIO. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Deprecate Auto EOI (end of interrupt). */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @} */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @name Hyper-V implementation hardware features.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * Which hardware features are in use by the hypervisor.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * @{
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** APIC overlay is used. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** MSR bitmaps is used. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Architectural performance counter supported. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Nested paging is used. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** DMA remapping is used. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Interrupt remapping is used. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Memory patrol scrubber is present. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @} */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @name Hyper-V MSRs.
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync * @{
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 0. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE0_START UINT32_C(0x40000000)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest OS identification (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Enable hypercall interface (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Virtual processor's (VCPU) index (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Reset operation (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 0. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE0_END MSR_GIM_HV_RESET
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 1. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE1_START UINT32_C(0x40000010)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Virtual processor's (VCPU) runtime (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 1. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE1_END MSR_GIM_HV_VP_RUNTIME
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 2. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE2_START UINT32_C(0x40000020)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Per-VM reference counter (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Per-VM TSC page (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Frequency of TSC in Hz as reported by the hypervisor (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 2. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE2_END MSR_GIM_HV_APIC_FREQ
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 3. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE3_START UINT32_C(0x40000070)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Access to APIC EOI (End-Of-Interrupt) register (W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Access to APIC ICR (Interrupt Command) register (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Access to APIC TPR (Task Priority) register (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Enables lazy EOI processing (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 3. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE3_END MSR_GIM_HV_APIC_ASSIST_PAGE
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 4. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE4_START UINT32_C(0x40000080)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Control behaviour of synthetic interrupt controller (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Synthetic interrupt controller version (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Base address of synthetic interrupt event flag (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Base address of synthetic interrupt parameter page (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** End-Of-Message in synthetic interrupt parameter page (W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 4. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE4_END MSR_GIM_HV_EOM
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 5. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE5_START UINT32_C(0x40000090)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 0 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 1 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 2 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 3 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 4 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 5 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 6 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 7 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 8 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 9 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 10 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 11 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 12 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 13 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 14 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures synthetic interrupt source 15 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 5. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE5_END MSR_GIM_HV_SINT15
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 6. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE6_START UINT32_C(0x400000B0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures register for synthetic timer 0 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Expiration time or period for synthetic timer 0 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures register for synthetic timer 1 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Expiration time or period for synthetic timer 1 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures register for synthetic timer 2 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Expiration time or period for synthetic timer 2 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configures register for synthetic timer 3 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Expiration time or period for synthetic timer 3 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 6. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE6_END MSR_GIM_HV_STIMER3_COUNT
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 7. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE7_START UINT32_C(0x400000C1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Trigger to transition to power state C1 (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Trigger to transition to power state C2 (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Trigger to transition to power state C3 (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 7. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE7_END MSR_GIM_HV_POWER_STATE_TRIGGER_C3
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 8. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE8_START UINT32_C(0x400000D1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configure the recipe for power state transitions to C1 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configure the recipe for power state transitions to C2 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Configure the recipe for power state transitions to C3 (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 8. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE8_END MSR_GIM_HV_POWER_STATE_CONFIG_C3
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 9. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE9_START UINT32_C(0x400000E0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Map the guest's retail partition stats page (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Map the guest's internal partition stats page (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Map the guest's retail VP stats page (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Map the guest's internal VP stats page (R/W) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 9. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE9_END MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 10. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE10_START UINT32_C(0x400000F0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Trigger the guest's transition to idle power state (R) */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Synthetic debug control. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Synthetic debug status. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Synthetic debug send buffer. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Synthetic debug receive buffer. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Synthetic debug pending buffer. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 10. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE10_END MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** Start of range 11. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE11_START UINT32_C(0x40000100)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest crash MSR 0. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest crash MSR 1. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest crash MSR 2. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest crash MSR 3. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest crash MSR 4. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** Guest crash control. */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync/** End of range 11. */
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsync#define MSR_GIM_HV_RANGE11_END MSR_GIM_HV_CRASH_CTL
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync/** @} */
5067a9619d7131c54d4ebb371d9dac91abdd34f6vboxsync
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE0_START <= MSR_GIM_HV_RANGE0_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE1_START <= MSR_GIM_HV_RANGE1_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE2_START <= MSR_GIM_HV_RANGE2_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE3_START <= MSR_GIM_HV_RANGE3_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE4_START <= MSR_GIM_HV_RANGE4_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE5_START <= MSR_GIM_HV_RANGE5_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE6_START <= MSR_GIM_HV_RANGE6_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE7_START <= MSR_GIM_HV_RANGE7_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE8_START <= MSR_GIM_HV_RANGE8_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE9_START <= MSR_GIM_HV_RANGE9_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
bc5cd42756b3f98351040bbfccc08dd9bacd103avboxsyncAssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
236b2935f217749893b7034e59da3e3568928acevboxsync
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync * @{
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync */
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync/** The hypercall enable bit. */
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync#define MSR_GIM_HV_RESET_BIT RT_BIT_64(0)
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync/** Whether the hypercall-page is enabled or not. */
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync#define MSR_GIM_HV_RESET_IS_SET(a) RT_BOOL((a) & MSR_GIM_HV_RESET_BIT)
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync/** @} */
157093a77f2752732368338110cb50fa6cd7717fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
157093a77f2752732368338110cb50fa6cd7717fvboxsync * @{
157093a77f2752732368338110cb50fa6cd7717fvboxsync */
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Guest-physical page frame number of the hypercall-page. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** The hypercall enable bit. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define MSR_GIM_HV_HYPERCALL_ENABLE_BIT RT_BIT_64(0)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Whether the hypercall-page is enabled or not. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define MSR_GIM_HV_HYPERCALL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_ENABLE_BIT)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** @} */
157093a77f2752732368338110cb50fa6cd7717fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
157093a77f2752732368338110cb50fa6cd7717fvboxsync * @{
157093a77f2752732368338110cb50fa6cd7717fvboxsync */
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Guest-physical page frame number of the TSC-page. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** The TSC-page enable bit. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define MSR_GIM_HV_REF_TSC_ENABLE_BIT RT_BIT_64(0)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Whether the TSC-page is enabled or not. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE_BIT)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** @} */
157093a77f2752732368338110cb50fa6cd7717fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Hyper-V page size. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define GIM_HV_PAGE_SIZE 0x1000
157093a77f2752732368338110cb50fa6cd7717fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync/**
157093a77f2752732368338110cb50fa6cd7717fvboxsync * MMIO2 region indices.
157093a77f2752732368338110cb50fa6cd7717fvboxsync */
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** The hypercall page region. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** The TSC page region. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** The maximum region index (must be <= UINT8_MAX). */
157093a77f2752732368338110cb50fa6cd7717fvboxsync#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
157093a77f2752732368338110cb50fa6cd7717fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync/**
157093a77f2752732368338110cb50fa6cd7717fvboxsync * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
157093a77f2752732368338110cb50fa6cd7717fvboxsync * page.
157093a77f2752732368338110cb50fa6cd7717fvboxsync */
157093a77f2752732368338110cb50fa6cd7717fvboxsynctypedef struct GIMHVREFTSC
157093a77f2752732368338110cb50fa6cd7717fvboxsync{
bc7fd0c97cf19d987daf12b1f4893bec2e2a7c96vboxsync uint32_t u32TscSequence;
bc7fd0c97cf19d987daf12b1f4893bec2e2a7c96vboxsync uint32_t uReserved0;
bc7fd0c97cf19d987daf12b1f4893bec2e2a7c96vboxsync uint64_t u64TscScale;
bc7fd0c97cf19d987daf12b1f4893bec2e2a7c96vboxsync int64_t i64TscOffset;
157093a77f2752732368338110cb50fa6cd7717fvboxsync} GIMHVTSCPAGE;
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync/** Pointer to Hyper-V reference TSC. */
157093a77f2752732368338110cb50fa6cd7717fvboxsynctypedef GIMHVREFTSC *PGIMHVREFTSC;
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync/** Pointer to a const Hyper-V reference TSC. */
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsynctypedef GIMHVREFTSC const *PCGIMHVREFTSC;
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync/**
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync * GIM Hyper-V VM instance data.
157093a77f2752732368338110cb50fa6cd7717fvboxsync * Changes to this must checked against the padding of the gim union in VM!
157093a77f2752732368338110cb50fa6cd7717fvboxsync */
157093a77f2752732368338110cb50fa6cd7717fvboxsynctypedef struct GIMHV
157093a77f2752732368338110cb50fa6cd7717fvboxsync{
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync /** @name MSRs.
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync * { */
157093a77f2752732368338110cb50fa6cd7717fvboxsync /** Guest OS identity MSR. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint64_t u64GuestOsIdMsr;
157093a77f2752732368338110cb50fa6cd7717fvboxsync /** Hypercall MSR. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint64_t u64HypercallMsr;
157093a77f2752732368338110cb50fa6cd7717fvboxsync /** Reference TSC page MSR. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint64_t u64TscPageMsr;
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync /** @} */
157093a77f2752732368338110cb50fa6cd7717fvboxsync
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync /** @name CPUID features.
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync * { */
157093a77f2752732368338110cb50fa6cd7717fvboxsync /** Basic features. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint32_t uBaseFeat;
157093a77f2752732368338110cb50fa6cd7717fvboxsync /** Partition flags. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint32_t uPartFlags;
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync /** Power management. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint32_t uPowMgmtFeat;
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync /** Miscellaneous. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint32_t uMiscFeat;
f8f484be8e0e78344ba79891ce9751c172517062vboxsync /** Hypervisor hints to the guest. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync uint32_t uHyperHints;
f8f484be8e0e78344ba79891ce9751c172517062vboxsync /** Hypervisor capabilities. */
f8f484be8e0e78344ba79891ce9751c172517062vboxsync uint32_t uHyperCaps;
8d1b88d15f8863c8c7312f9b0738587e5d3ff6f1vboxsync /** @} */
157093a77f2752732368338110cb50fa6cd7717fvboxsync
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync RTSPINLOCK hSpinlockR0;
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync#if HC_ARCH_BITS == 32
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync uint32_t u32Alignment1;
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync#endif
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync /** Array of MMIO2 regions. */
157093a77f2752732368338110cb50fa6cd7717fvboxsync GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
157093a77f2752732368338110cb50fa6cd7717fvboxsync} GIMHV;
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Pointer to per-VM GIM Hyper-V instance data. */
157093a77f2752732368338110cb50fa6cd7717fvboxsynctypedef GIMHV *PGIMHV;
157093a77f2752732368338110cb50fa6cd7717fvboxsync/** Pointer to const per-VM GIM Hyper-V instance data. */
157093a77f2752732368338110cb50fa6cd7717fvboxsynctypedef GIMHV const *PCGIMHV;
157093a77f2752732368338110cb50fa6cd7717fvboxsyncAssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
2ac3892cdc8b16a0dee55e8b4510b8ecea83c95fvboxsyncAssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
157093a77f2752732368338110cb50fa6cd7717fvboxsync
236b2935f217749893b7034e59da3e3568928acevboxsyncRT_C_DECLS_BEGIN
236b2935f217749893b7034e59da3e3568928acevboxsync
157093a77f2752732368338110cb50fa6cd7717fvboxsync#ifdef IN_RING0
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR0_INT_DECL(int) gimR0HvInitVM(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR0_INT_DECL(int) gimR0HvTermVM(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset);
157093a77f2752732368338110cb50fa6cd7717fvboxsync#endif /* IN_RING0 */
157093a77f2752732368338110cb50fa6cd7717fvboxsync
236b2935f217749893b7034e59da3e3568928acevboxsync#ifdef IN_RING3
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvInit(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(PGIMMMIO2REGION) gimR3HvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM, uint32_t uSSMVersion);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsync
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
236b2935f217749893b7034e59da3e3568928acevboxsync#endif /* IN_RING3 */
236b2935f217749893b7034e59da3e3568928acevboxsync
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
f84ab9e4599e758ec1f36479f871b3f5b7f271f2vboxsyncVMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
236b2935f217749893b7034e59da3e3568928acevboxsync
236b2935f217749893b7034e59da3e3568928acevboxsyncRT_C_DECLS_END
236b2935f217749893b7034e59da3e3568928acevboxsync
34ec9190905fd23efbc30d37557991a1889a33e7vboxsync#endif
236b2935f217749893b7034e59da3e3568928acevboxsync