/illumos-gate/usr/src/uts/sun4u/os/ |
H A D | mach_startup.c | 82 * the CPU halt support. The cpu_halt_cpu() support is provided 95 * The probe fires when the CPU undergoes an idle state change (e.g. halting) 96 * The agument passed is the state to which the CPU is transitioning. 110 intr_init(CPU); /* init interrupt request free list */ 221 * Halt the present CPU until awoken via an interrupt. 228 cpu_t *cpup = CPU; 236 * If this CPU is online then we should notate our halting 237 * by adding ourselves to the partition's halted CPU 241 if (CPU->cpu_flags & CPU_OFFLINE) 254 * this CPU remain [all...] |
/illumos-gate/usr/src/uts/i86pc/os/ |
H A D | mp_startup.c | 83 struct cpu cpus[1]; /* CPU data */ 120 * Init CPU info - get CPU type info for processor_info system call. 128 * Get clock-frequency property for the CPU. 152 * If called for the BSP, cp is equal to current CPU. 154 * of current CPU as default values for cpu_idstr and cpu_brandstr. 156 * has been invoked on target CPU. 158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); 159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); 163 * Configure syscall support on this CPU [all...] |
H A D | mp_machdep.c | 425 (*CPU->cpu_m.mcpu_idle_cpu)(); 429 * Function called by CPU idle notification framework to check whether CPU 431 * If CPU has been awakened, call cpu_idle_exit() to notify CPU idle 440 * If interrupt happened, do_interrupt() will notify CPU idle 449 * Idle the present CPU until wakened via an interrupt 454 cpu_t *cpup = CPU; 460 * If this CPU is online, and there's multiple CPUs 462 * by adding ourselves to the partition's halted CPU [all...] |
H A D | timestamp.c | 56 * timestamp counter ("TSC") which increments once per CPU cycle. The contents 86 * have newly onlined CPUs call tsc_sync_slave(), while the CPU performing 205 * another CPU, and we have drifted just enough so that 247 * adding the CPU's TSC tick delta. Note that disabling 255 tsc = tsc_read() + tsc_sync_tick_delta[CPU->cpu_id]; 283 hrt = tsc_sync_tick_delta[CPU->cpu_id]; 306 * migrated between the tsc_read() and adding the CPU's 314 tsc += tsc_sync_tick_delta[CPU->cpu_id]; 338 * tsc_tick() running on another CPU -- or it may be because 356 * the CPU' [all...] |
H A D | intr.c | 68 * interrupts (IPI) which are the basis for CPU cross calls and CPU pokes. 206 * current CPU contains a number of kernel threads (kthread_t) that can be used 216 * interrupts, but the notification vector is different. Each CPU has a bitmask 217 * of pending software interrupts. We can notify a CPU to process software 510 struct cpu *cpu = CPU; 589 * Store starting timestamp in CPU structure for this PIL. 717 * allocate one for each level on each CPU. 804 * this interrupt thread back on the CPU's free list and 813 * Set CPU' [all...] |
H A D | startup.c | 809 cpuid_pass2(CPU); 831 CPU->cpu_brandstr); 1073 cpuid_get_addrsize(CPU, &pabits, NULL); 1222 (void) getl2cacheinfo(CPU, 1509 CPU->cpu_m.mcpu_evt_pend = &cpu0_evt_data; 1571 CPU->cpu_m.mcpu_vcpu_info = 1572 &HYPERVISOR_shared_info->vcpu_info[CPU->cpu_id]; 1753 * Set up the CPU module subsystem for the boot cpu in the native 1782 (hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1783 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandi [all...] |
H A D | cmi.c | 28 * Public interface to routines implemented by CPU modules 86 * CPU modules have a filenames such as "cpu.AuthenticAMD.15" and 159 * Hold the module in memory. We call to CPU modules without using the 704 if ((hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 705 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) == NULL || 710 CPU->cpu_id, 782 if ((hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 783 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) [all...] |
/illumos-gate/usr/src/uts/intel/dtrace/ |
H A D | dtrace_isa.c | 51 uintptr_t caller = CPU->cpu_dtrace_caller; 53 if ((on_intr = CPU_ON_INTR(CPU)) != 0) 54 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME)); 122 (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags; 144 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp; 194 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp; 308 (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags; 513 if ((on_intr = CPU_ON_INTR(CPU)) != 0) 514 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME)); 661 cpu_core[CPU [all...] |
/illumos-gate/usr/src/uts/sun4/os/ |
H A D | intr.c | 164 CPU->cpu_m.poke_cpu_outstanding = B_FALSE; 209 * Generates softlevel1 interrupt on current CPU if it 220 * use per-CPU siron inum. 222 if (siron_cpu_inum && siron_cpu_inum[CPU->cpu_id] != 0) 223 inum = siron_cpu_inum[CPU->cpu_id]; 238 * the work is done when CPU is configured. 244 * This routine creates per-CPU siron inum for CPUs which are 253 * Get the memory for per-CPU siron inums 280 * This routine generates a cross-call on target CPU(s). 285 int cpuid = CPU [all...] |
H A D | mp_startup.c | 74 * Amount of time (in milliseconds) we should wait before giving up on CPU 75 * initialization and assuming that the CPU we're trying to wake up is dead 104 * Allocate and initialize the startup thread for this CPU. 111 * as soon as the CPU comes online. 142 * The dispatcher may discover the CPU before it is in cpu_ready_set 143 * and attempt to poke it. Before the CPU is in cpu_ready_set, any 146 * requests for this CPU. Pokes that come in before the CPU is in 147 * cpu_ready_set can be ignored because the CPU is about to come 220 * a CPU [all...] |
/illumos-gate/usr/src/uts/common/inet/sctp/ |
H A D | sctp_stack.h | 103 /* Per CPU SCTP statistics counters. */ 111 ((sctps)->sctps_sc[CPU->cpu_seqid]->sctp_sc_stats.x++) 114 BUMP_MIB(&(sctps)->sctps_sc[CPU->cpu_seqid]->sctp_sc_mib, x) 117 UPDATE_MIB(&(sctps)->sctps_sc[CPU->cpu_seqid]->sctp_sc_mib, x, y) 182 * Per CPU stats 184 * sctps_sc: array of pointer to per CPU stats. The i-th element in 185 * the array represents the stats of the CPU with cpu_seqid. 186 * sctps_sc_cnt: number of CPU stats in the sctps_sc array.
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/illumos-gate/usr/src/uts/common/disp/ |
H A D | disp.c | 84 /* routines invoked when a CPU enters/exits the idle loop */ 98 disp_t cpu0_disp; /* boot CPU's dispatch queue */ 119 * on the CPU to be considered loosely-bound to that CPU to reduce 127 * be sitting on a run queue before it can be stolen by another CPU 179 * Allocate new kp queues for each CPU partition. 184 * Allocate new dispatch queues for each CPU. 222 CPU->cpu_disp->disp_maxrunpri = -1; 223 CPU->cpu_disp->disp_max_unbound_pri = -1; 226 * Initialize the default CPU partitio [all...] |
/illumos-gate/usr/src/lib/fm/topo/libtopo/common/ |
H A D | topo_hc.h | 49 #define CPU "cpu" macro
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/illumos-gate/usr/src/cmd/picl/plugins/sun4u/snowbird/conf/ |
H A D | SUNW,Netra-CP2300.RTM.conf | 29 NODE CPU location 32 PROP Label string r 0 "CPU" 36 NODE CPU fru
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H A D | SUNW,Netra-CP2300.conf | 29 NODE CPU location 32 PROP Label string r 0 "CPU" 36 NODE CPU fru
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/illumos-gate/usr/src/uts/common/fs/zfs/sys/ |
H A D | zfs_context.h | 76 #define CPU_SEQID (CPU->cpu_seqid)
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/illumos-gate/usr/src/uts/i86pc/io/ |
H A D | cbe.c | 74 cyclic_softint(CPU, CY_LOCK_LEVEL); 81 cpu_t *cpu = CPU; 96 cpu_t *cpu = CPU; 180 if (dest == CPU) { 266 * disabled on CPU 0, and cbe_enable is called when we resume.
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H A D | hpet_acpi.c | 99 static hpet_proxy_t *hpet_proxy_users; /* one per CPU */ 1001 * This ISR runs on one CPU which pokes other CPUs out of Deep C-state as 1039 * the HPET. The CPU running this ISR will NEVER find itself in the 1042 ASSERT(hpet_proxy_users[CPU->cpu_id] == HPET_INFINITY); 1083 if (id != CPU->cpu_id) 1116 * Find the next CPU to wake up and next HPET program time. 1120 next_proxy_id = CPU->cpu_id; 1124 if (id != CPU->cpu_id) 1148 * We are gambling some CPU will attempt to enter a 1168 * next CPU [all...] |
/illumos-gate/usr/src/uts/sun4u/starcat/ml/ |
H A D | starcat_asm.s | 65 ! Load the mc_decode reg for this CPU.
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/illumos-gate/usr/src/uts/sun4u/cpu/ |
H A D | us3_common.c | 92 * Per CPU pointers to physical address of TL>0 logout data areas. 105 * Per CPU pending error at TL>0, used by level15 softint handler 227 #define S003 149 /* Syndrome 0x003 => likely from CPU/EDU:ST/FRU/BP */ 232 #define S071 150 /* Syndrome 0x071 => likely from WDU/CPU */ 779 * 3) when the CPU that holds the TSB mapping locked tries to 781 * us or the CPU we're trying to recover, and will in turn 888 * even for a different target CPU. 919 CHEETAH_LIVELOCK_ENTRY_SET(histp, buddy, CPU->cpu_id); 994 * This is called by the cyclic framework when this CPU becomes online 1047 if ((CPU [all...] |
/illumos-gate/usr/src/uts/common/os/ |
H A D | ftrace.c | 45 * ftrace_nent - size of the per-CPU event ring buffer. 76 * Per-CPU Tracing State: 127 * Check whether a CPU is installed. 138 * being false - e.g. when a CPU is DR'ed in. 368 cp = CPU; 402 cp = CPU; 437 cp = CPU; 473 cp = CPU; 508 cp = CPU;
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/illumos-gate/usr/src/uts/sun4u/starfire/io/ |
H A D | idn_xf.c | 191 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); 210 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); 229 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); 236 if (pc_prep_cic_buffer(CPU->cpu_id, (uint_t)sm_mask) < 0) 268 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); 296 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); 305 if (pc_prep_cic_buffer(CPU->cpu_id, sm_bar_msb) < 0) 332 if (pc_prep_cic_buffer(CPU->cpu_id, sm_bar_lsb) < 0) 364 ASSERT(CPUID_TO_BOARDID(CPU->cpu_id) == board); 392 ASSERT(CPUID_TO_BOARDID(CPU [all...] |
/illumos-gate/usr/src/uts/sparc/dtrace/ |
H A D | dtrace_isa.c | 281 if ((on_intr = CPU_ON_INTR(CPU)) != 0) 282 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME)); 368 (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags; 396 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp; 433 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp; 710 if ((on_intr = CPU_ON_INTR(CPU)) != 0) 711 stacktop = (struct frame *)CPU->cpu_intr_stack + SA(MINFRAME); 881 if (cpu_core[CPU->cpu_id].cpuc_dtrace_flags & CPU_DTRACE_FAULT) 901 if (cpu_core[CPU->cpu_id].cpuc_dtrace_flags & CPU_DTRACE_FAULT)
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/illumos-gate/usr/src/uts/i86xpv/os/ |
H A D | mp_xen.c | 28 * Virtual CPU management. 46 * The hypervisor has two notions of CPU states as represented in the store: 50 * "online": the VCPU is running. Corresponds to a CPU state other than 53 * Currently, only a notification via xenstore can bring a CPU into a 60 * play nice, we don't allow it. Thus, any attempt to power on/off a CPU is 66 * (since we are just about to remove its ability to run on a real CPU, 67 * possibly forever). However, an offline CPU in Solaris can take 82 * Thus, we set CPU_PHASE_WAIT_SAFE for every powered-on CPU, as well as 83 * poking them to make sure they're not blocked[1]. When every CPU has 85 * know we can suspend, or power-off a CPU, withou [all...] |
/illumos-gate/usr/src/uts/sun4/ml/ |
H A D | swtch.s | 68 * is a zombie and must be put on the deathrow list after the CPU is 104 ldn [THREAD_REG + T_CPU], %i1 ! get CPU pointer 129 ! i1 = CPU ptr 174 stn %o0, [%i1 + CPU_THREAD] ! set CPU's thread to idle 260 mov %i1, %o2 ! %o2 = CPU 273 mov %i1, %o2 ! %o2 = CPU 296 ! Fix CPU structure to indicate new running thread. 297 ! Set pointer in new thread to the CPU structure. 300 ldx [%i0 + T_CPU], %g2 ! last CPU to run the new thread 307 stx %i1, [%i0 + T_CPU] ! set new thread's CPU pointe [all...] |