Cross Reference: /illumos-gate/usr/src/uts/i86pc/os/intr.c

Lines Matching refs:CPU
68  * interrupts (IPI) which are the basis for CPU cross calls and CPU pokes.
206  * current CPU contains a number of kernel threads (kthread_t) that can be used
216  * interrupts, but the notification vector is different. Each CPU has a bitmask
217  * of pending software interrupts. We can notify a CPU to process software
510 	struct cpu *cpu = CPU;
589 	 * Store starting timestamp in CPU structure for this PIL.
717 	 * allocate one for each level on each CPU.
804 		 * this interrupt thread back on the CPU's free list and
813 		 * Set CPU's base SPL based on active interrupts bitmask
869  * handling all interrupts at the specified pil on this CPU. It is
896  * Whenever interrupts arrive on a CPU which is handling a lower pil
914 	cpu = CPU;
963 	 * CPU might get preempted just after the address computation,
964 	 * but just before the atomic transaction, so another CPU would
965 	 * actually set the original CPU's st_pending bit.  However,
973 	 * disabled on -this- CPU.  This code would probably be cheaper:
996 	 * allocate one for each level on the CPU.
1033 	 * Set bit for this pil in CPU's interrupt active bitmask.
1076 		 * This was an interrupt thread, so set CPU's base SPL.
1124  * Create interrupt kstats for this CPU.
1166  * Delete interrupt kstats for this CPU.
1175  * Convert interrupt statistics from CPU ticks to nanoseconds and
1231 		cpu = CPU;
1276 	struct cpu *cpu = CPU;
1295 	struct cpu *cpu = CPU;
1315 	struct cpu *cpu = CPU;
1341 	struct cpu *cpu = CPU;
1432 	tp = CPU->cpu_thread;
1443 			trap(rp, (caddr_t)0, CPU->cpu_id);
1480 	if (CPU->cpu_kprunrun && (rp->r_ps & PS_IE)) {
1533  * We are careful not to set priority lower than CPU->cpu_base_pri,
1536  * and look at CPU->cpu_base_pri
1546 	cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
1576 	cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
1600 	return (CPU->cpu_m.mcpu_pri);