Searched refs:CPU (Results 126 - 150 of 299) sorted by relevance

1234567891011>>

/illumos-gate/usr/src/uts/sun4v/os/
H A Dsuspend.c132 * When non-zero, after a successful suspend and resume, cpunodes, CPU HW
142 * registers on one CPU over a suspend/resume. Other CPUs may experience
151 * all CPU's %tick and %stick will advance forwards as long as, across all
241 * respectively. Let x be the maximum difference between any two CPU's %stick
275 * guarantees any processes bound to CPU P0 or P1 will not see a %stick
300 * this CPU, add an additional value. Multiply the %tick/%stick
306 (CPU->cpu_curr_clock * suspend_tick_stick_max_delta * 2 / MICROSEC);
322 * Set the {tick,stick}.NPT field to 1 on this CPU.
332 * Synchronize a CPU's {tick,stick}.NPT fields with the current state
333 * of the system. This is used when a CPU i
[all...]
/illumos-gate/usr/src/uts/sun4u/os/
H A Dmach_trap.c263 ptl1_state_t *pstate = &CPU->cpu_m.ptl1_state;
307 ptl1_state_t *pstate = &CPU->cpu_m.ptl1_state;
/illumos-gate/usr/src/uts/intel/kdi/
H A Dkdi_idt.c36 * the active CPU when we're in kmdb so we can handle things like page faults
52 * The last phase of boot-loaded KMDB activation occurs at non-boot CPU
53 * startup. We will be called on each non-boot CPU, thus allowing us to set up
54 * any watchpoints that may have been configured on the boot CPU and interpose
55 * on the given CPU's IDT. We don't save the interposed descriptors in this
62 * each CPU's IDT. We save the handlers we replace, both for deactivation and
66 * rather than just modifying the IDT table from the CPU running kdi_activate().
255 kdi_kgates[i] = CPU->cpu_m.mcpu_idt[vec];
382 * Activation for CPUs other than the boot CPU, called from that CPU'
[all...]
/illumos-gate/usr/src/uts/sun4u/ngdr/io/
H A Ddr_quiesce.c580 if (tp->t_state == TS_ONPROC && tp->t_cpu != CPU)
721 CPU->cpu_id);
750 CPU->cpu_id);
817 CPU_SIGNATURE(OS_SIG, SIGST_RUN, SIGSUBST_NULL, CPU->cpu_id);
839 CPU->cpu_id);
935 CPU_SIGNATURE(OS_SIG, SIGST_QUIESCED, SIGSUBST_NULL, CPU->cpu_id);
/illumos-gate/usr/src/uts/common/syscall/
H A Drw.c183 cp = CPU;
312 cp = CPU;
458 cp = CPU;
592 cp = CPU;
751 cp = CPU;
901 cp = CPU;
1088 cp = CPU;
1297 cp = CPU;
1423 cp = CPU;
1551 cp = CPU;
[all...]
/illumos-gate/usr/src/uts/i86pc/vm/
H A Dhtable.c1940 * pfn as we last used referenced from this CPU.
1979 * Disable preemption and grab the CPU's hci_mutex
1982 ASSERT(CPU->cpu_hat_info != NULL);
1983 mutex_enter(&CPU->cpu_hat_info->hci_mutex);
1984 x = PWIN_TABLE(CPU->cpu_id);
2045 * Drop the CPU's hci_mutex and restore preemption.
2055 va = (uintptr_t)PWIN_VA(PWIN_TABLE(CPU->cpu_id));
2060 mutex_exit(&CPU->cpu_hat_info->hci_mutex);
2367 * Acquire access to the CPU pagetable windows for the dest and source.
2374 uint_t x = PWIN_SRC(CPU
[all...]
H A Dhat_i86.c423 ASSERT(CPU->cpu_current_hat != hat);
500 cpuid_opteron_erratum(CPU, 6671130)) {
531 * If CPU enabled the page table global bit, use it for the kernel
548 * Use CPU info to set various MMU parameters
550 cpuid_get_addrsize(CPU, &pa_bits, &va_bits);
737 CPUSET_ADD(khat_cpuset, CPU->cpu_id);
772 * Prepare CPU specific pagetables for VLP processes on 64 bit kernels.
774 * Each CPU has a set of 2 pagetables that are reused for any 32 bit
917 * the "per CPU" page tables for VLP processes.
931 hat_vlp_setup(CPU);
[all...]
/illumos-gate/usr/src/uts/common/os/
H A Dcpu.c27 * Architecture-independent CPU control functions.
131 * Maximum possible CPU id. This can never be >= NCPU since NCPU is
132 * used to size arrays that are indexed by CPU id.
147 * CPU that we're trying to offline. Protected by cpu_lock.
388 * Set affinity for a specified CPU.
395 * by thread_affinity_set and CPU->cpu_id will be the target CPU.
407 cpu_id = CPU->cpu_id;
432 * Make sure we're running on the right CPU.
455 * clear the CPU affinit
[all...]
H A Dsched.c539 struct cpu *cpup = CPU;
635 struct cpu *cpup = CPU;
750 * saves CPU cycles as the number of pages that are
831 struct cpu *cpup = CPU;
H A Dvm_pageout.c104 * equivalent of some underlying %CPU duty cycle.
106 * awakened every 25 clock ticks. So, converting from %CPU to ticks
173 * timed out (exceeded its CPU budget), rather than because it visited
338 * could lead to thrashing and higher CPU usage.
342 * time for scanning on slow CPU's and avoid thrashing, as a
343 * result of scanning too many pages, on faster CPU's.
347 * of the CPU) on some of the following machines that currently
368 * limited to using ~4% of the CPU. This results in increasing
400 * the fact that user processes running on other CPU's can be
403 * more than one CPU t
[all...]
H A Dturnstile.c110 * priority inheritance to everyone in its way, and yields the CPU.
450 ASSERT(t != CPU->cpu_idle_thread);
451 ASSERT(CPU_ON_INTR(CPU) == 0);
/illumos-gate/usr/src/uts/sun4/io/
H A Dtrapstat.c76 * (Note that per-CPU statistics fall out by creating a different trap table
77 * for each CPU.)
236 * branch displacement; if each CPU were to consume a disjoint virtual range
241 * each CPU were to consume a disjoint virtual range, we would have an
246 * solve this by not permitting each CPU to consume a disjoint virtual range.
247 * Rather, we have each CPU's interposing trap table use the _same_ virtual
273 * by reducing the virtual address space requirements per CPU via shared
278 * | CPU 1015 trap statistics (4KB) | .
284 * | CPU 1 trap statistics (4KB) | .
286 * | CPU
[all...]
/illumos-gate/usr/src/uts/i86pc/cpu/amd_opteron/
H A Dao_mca.c407 uint_t procnodeid = pg_plat_hw_instance_id(CPU, PGHW_PROCNODE);
469 uint_t procnodeid = pg_plat_hw_instance_id(CPU, PGHW_PROCNODE);
502 uint_t procnodeid = pg_plat_hw_instance_id(CPU, PGHW_PROCNODE);
/illumos-gate/usr/src/uts/sun4u/starcat/os/
H A Dstarcat.c108 * value of max_ncpus [see PSARC 1997/165 CPU Dynamic Reconfiguration].
156 /* Set the CPU signature function pointer */
288 return (starcat_mem_per_board); /* each CPU has a memory controller */
344 * Find the CPU associated with a slice at boot-time.
367 * Starcat memory controller portid == global CPU id
392 * belongs to this CPU/CMP or a different one.
394 if (portid == cpunodes[CPU->cpu_id].portid)
404 * If the memory controller is local to this CPU, we use
492 * Return the platform handle for the lgroup containing the given CPU
509 * Return the real platform handle for the CPU unti
[all...]
/illumos-gate/usr/src/uts/sun4v/pcbe/
H A Dniagara2_pcbe.c574 * If this is a static per-CPU configuration, the CPC
576 * CPU. If this is a per-LWP configuration, the driver
577 * ensures no static per-CPU counting is ongoing and that
708 ni2_cpc_counting[CPU->cpu_id] = B_TRUE;
736 ni2_cpc_counting[CPU->cpu_id] = B_FALSE;
788 if (ni2_cpc_counting[CPU->cpu_id] &&
/illumos-gate/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu_asm.s87 * currently running on this CPU.
102 ! } else if (current CPU tsbmiss->usfmmup != victim sfmmup) {
371 CPU_ADDR(%o2, %o4) ! load CPU struct addr to %o2 using %o4
391 ldub [%o0 + SFMMU_TTEFLAGS], %o3 ! per-CPU tsbmiss area.
/illumos-gate/usr/src/uts/intel/pcbe/
H A Dopteron_pcbe.c438 amd_family = cpuid_getfamily(CPU);
445 if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf)
465 rev = cpuid_getchiprev(CPU);
H A Dp123_pcbe.c520 * CPU reference strings
543 * Discover type of CPU and set events pointer appropriately.
551 if (cpuid_getvendor(CPU) != X86_VENDOR_Intel)
553 switch (cpuid_getfamily(CPU)) {
559 if (cpuid_getmodel(CPU) < 4)
/illumos-gate/usr/src/uts/i86pc/i86hvm/io/xpv/
H A Dxpv_support.c625 SUSPEND_DEBUG("%d: xen_shutdown_handler: \"%s\"\n", CPU->cpu_id, str);
650 SUSPEND_DEBUG("%d: trying again\n", CPU->cpu_id);
/illumos-gate/usr/src/uts/sun4u/serengeti/io/
H A Dsbdp_mem.c383 linesize = cpunodes[CPU->cpu_id].ecache_linesize;
428 SBDP_DBG_MEM("cpu %d\n", CPU->cpu_id);
759 ASSERT(curthread->t_bound_cpu == CPU);
760 if (SG_CPUID_TO_PORTID(CPU->cpu_id) == portid) {
1081 csize = (size_t)(cpunodes[CPU->cpu_id].ecache_size * 2);
1082 linesize = (size_t)(cpunodes[CPU->cpu_id].ecache_linesize);
1545 if (portid == cpunodes[CPU->cpu_id].portid)
1554 * If the memory controller is local to this CPU, we use
1599 if (portid == cpunodes[CPU->cpu_id].portid)
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dopl_olympus.c127 * UE is classified into four classes (MEM, CHANNEL, CPU, PATH).
367 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped);
376 * CPUs, set "index" to the highest numbered CPU in
394 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids);
538 cmn_err(CE_PANIC, "CPU%d Impl %d: Only SPARC64-VI(I) is "
679 CPU_STATS_ADDQ(CPU, sys, xcalls, 1);
1022 * post-process CPU events that are dequeued. As such, it can be invoked
1024 * panic flow. We decode the CPU-specific data, and take appropriate actions.
1276 CPU->cpu_id, flt_in_memory, flt_status, unum, UNUM_NAMLEN, lenp);
1351 flush_ecache(ecache_flushaddr, cpunodes[CPU
[all...]
/illumos-gate/usr/src/uts/i86xpv/io/psm/
H A Dxpv_uppc.c237 * any missed operations (e.g. bind to CPU)
760 cpu_t *cpu = CPU;
823 struct cpu *cpu = CPU;
/illumos-gate/usr/src/uts/sun4/ml/
H A Dinterrupt.s377 ldn [THREAD_REG + T_CPU], %o2 ! delay - load CPU pointer
447 ! for each level on the CPU.
454 ldn [%o3 + T_LINK], %o4 ! unlink thread from CPU's list
457 ! Set bit for this level in CPU's active interrupt bitmask.
464 ! ASSERT(!(CPU->cpu_intr_actv & (1 << PIL)))
653 ! If our CPU is quiesced, we cannot preempt because the idle thread
717 ! Clear bit for this level in CPU's interrupt active bitmask.
723 ! ASSERT(CPU->cpu_intr_actv & (1 << PIL))
804 ! on the CPU's free list and resume the idle thread which will dispatch
842 ! Set the CPU'
[all...]
/illumos-gate/usr/src/cmd/mdb/sparc/v9/kmdb/
H A Dkaif_startup.s86 * Calculate the address of the save area for the current CPU. This
87 * would be a macro, but for need to call platform-specific CPU ID
89 * for CPU ID retrieval, which we call here. The retrieval code returns
183 1: /* CPU save area address is now in %g6 */
196 * CPU uses OBP's table at a time. We do this by waiting until we've
199 * Single-step is a bit different. Everything about the CPU's state is
276 * switch to the CPU-specific stack. We'll use this stack to finish
339 * 1. (common case) - intentional entry by a CPU intending to be the
340 * master. The CPU may have encountered a watchpoint, a breakpoint,
341 * or a programmed entry trap, and is *NOT* coming from OBP. The CPU
[all...]
/illumos-gate/usr/src/uts/common/cpr/
H A Dcpr_uthread.c158 if (tp->t_state == TS_ONPROC && tp->t_cpu != CPU)
305 * This should be called while CPU's are paused, and the caller is

Completed in 102 milliseconds

1234567891011>>