Lines Matching refs:CPU
423 ASSERT(CPU->cpu_current_hat != hat);
500 cpuid_opteron_erratum(CPU, 6671130)) {
531 * If CPU enabled the page table global bit, use it for the kernel
548 * Use CPU info to set various MMU parameters
550 cpuid_get_addrsize(CPU, &pa_bits, &va_bits);
737 CPUSET_ADD(khat_cpuset, CPU->cpu_id);
772 * Prepare CPU specific pagetables for VLP processes on 64 bit kernels.
774 * Each CPU has a set of 2 pagetables that are reused for any 32 bit
917 * the "per CPU" page tables for VLP processes.
931 hat_vlp_setup(CPU);
988 cpu_t *cpu = CPU;
1002 * Add this CPU to the active set for this HAT.
1055 ASSERT(cpu == CPU);
1367 cpu_t *cpu = CPU;
1737 * HAT_STRICTORDER: the CPU must issue the references in order, as the
1739 * HAT_UNORDERED_OK: the CPU may reorder the references (this is all kinds
1741 * HAT_MERGING_OK: merging and batching: the CPU may merge individual stores
1746 * HAT_LOADCACHING_OK: the CPU may cache the data it fetches and reuse it
1749 * HAT_STORECACHING_OK: the CPU may keep the data in the cache and push it to
1920 * the current CPU or flush all mappings in TLB.
1931 * If the target hat isn't the kernel and this CPU isn't operating
1934 if (hat != kas.a_hat && hat != CPU->cpu_current_hat)
1954 x86pte_t *vlpptep = CPU->cpu_hat_info->hci_vlp_l2ptes;
1958 reload_pae32(hat, CPU);
1993 * Record that a CPU is going idle
1998 atomic_or_ulong((ulong_t *)&CPU->cpu_m.mcpu_tlb_info, TLB_CPU_HALTED);
2014 tlb_info = CPU->cpu_m.mcpu_tlb_info;
2016 ASSERT(CPU->cpu_current_hat == kas.a_hat);
2021 while ((found = CAS_TLB_INFO(CPU, tlb_info, 0)) != tlb_info) {
2089 CPUSET_ONLY(justme, CPU->cpu_id);
2142 CPUSET_ADD(cpus_to_shootdown, CPU->cpu_id);
2465 * Invalidate a virtual address translation on a slave CPU during
3860 * Prepare for a CPU private mapping for the given address.
3862 * The address can only be used from a single CPU and can be remapped
3909 * Release a CPU private mapping for the given address.
3951 * Apply a temporary CPU private mapping to a page. We flush the TLB only
3952 * on this CPU, so this ought to have been called with preemption disabled.
3967 * on this CPU.
4029 if (cpup != CPU) {
4043 ASSERT(cpup != CPU);
4064 * On 1st CPU we can unload the prom mappings, basically we blow away