Lines Matching refs:CPU
377 ldn [THREAD_REG + T_CPU], %o2 ! delay - load CPU pointer
447 ! for each level on the CPU.
454 ldn [%o3 + T_LINK], %o4 ! unlink thread from CPU's list
457 ! Set bit for this level in CPU's active interrupt bitmask.
464 ! ASSERT(!(CPU->cpu_intr_actv & (1 << PIL)))
653 ! If our CPU is quiesced, we cannot preempt because the idle thread
717 ! Clear bit for this level in CPU's interrupt active bitmask.
723 ! ASSERT(CPU->cpu_intr_actv & (1 << PIL))
804 ! on the CPU's free list and resume the idle thread which will dispatch
842 ! Set the CPU's base SPL level.
846 ! ASSERT(!(CPU->cpu_intr_actv & (1 << PIL)))
864 call _intr_set_spl ! set CPU's base SPL level
958 ! Set bit for this level in CPU's active interrupt bitmask.
965 ! ASSERT(!(CPU->cpu_intr_actv & (1 << PIL)))
1059 ! We need to find the CPU offset of the cumulative counter. We start
1150 ! Store starting timestamp for this PIL in CPU structure at
1211 ! %o3 = CPU pointer
1216 ! Clear bit for this level in CPU's interrupt active bitmask.
1223 ! ASSERT(CPU->cpu_intr_actv & (1 << PIL))
1295 ! o3 = CPU pointer
1303 ! returned. Store a starting timestamp for it in the CPU structure.
1760 ! CPU softint priority queue, and compose the final softint pil mask.
1927 * Set CPU's base SPL level, based on which interrupt levels are active.
1940 ldn [THREAD_REG + T_CPU], %o2 ! load CPU pointer
1945 * %o2 = pointer to CPU
2092 * handling all interrupts at the specified pil on this CPU. It is
2119 * Whenever interrupts arrive on a CPU which is handling a lower pil