25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER START
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The contents of this file are subject to the terms of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Common Development and Distribution License (the "License").
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You may not use this file except in compliance with the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * See the License for the specific language governing permissions
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and limitations under the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * When distributing Covered Code, include this CDDL HEADER in each
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If applicable, add the following below this CDDL HEADER, with the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * fields enclosed by brackets "[]" replaced with your own identifying
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * information: Portions Copyright [yyyy] [name of copyright owner]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER END
c9d93b537520c235a6d4a0af53b9bf07cf3390e9James Anderson * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Use is subject to license terms.
e98fafb9956429b59c817d4fbd27720c73879203jl * Support for Olympus-C (SPARC64-VI) and Jupiter (SPARC64-VII).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Internal functions.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void cpu_payload_add_aflt(struct async_flt *, nvlist_t *, nvlist_t *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void opl_cpu_sync_error(struct regs *, ulong_t, ulong_t, uint_t, uint_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic int cpu_flt_in_memory(opl_async_flt_t *, uint64_t);
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmbstatic void opl_ta3();
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimandstatic int plat_prom_preserve_kctx_is_supported(void);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Error counters resetting interval.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * PA[22:0] represent Displacement in Jupiter
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * configuration space.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * set in /etc/system to control logging of user BERR/TO's
e98fafb9956429b59c817d4fbd27720c73879203jl * Set to 1 if booted with all Jupiter cpus (all-Jupiter features enabled).
1426d65aa9264a283c76d271972aeb7f6a070be3sm * The sfmmu_cext field to be used by processes in a shared context domain.
1426d65aa9264a283c76d271972aeb7f6a070be3smstatic uchar_t shctx_cext = TAGACCEXT_MKSZPAIR(DEFAULT_ISM_PAGESZC, TTE8K);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Olympus error log
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmb * OPL ta 3 save area.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * UE is classified into four classes (MEM, CHANNEL, CPU, PATH).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * No any other ecc_type_info insertion is allowed in between the following
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * four UE classess.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl SFSR_BERR, "BERR ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl SFSR_TO, "TO ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl SFSR_TLB_MUL, "TLB_MUL ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl SFSR_TLB_PRT, "TLB_PRT ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IAUG_CRE, "IAUG_CRE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_TSBP, "IUG_TSBP", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_PSTATE, "IUG_PSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_TSTATE, "IUG_TSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_F, "IUG_F", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_R, "IUG_R", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_AUG_SDC, "AUG_SDC", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_WDT, "IUG_WDT", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_DTLB, "IUG_DTLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_IUG_ITLB, "IUG_ITLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_MULTI_DAE, "MULTI_DAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_MULTI_IAE, "MULTI_IAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl UGESR_MULTI_UGE, "MULTI_UGE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep,
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmb * Setup trap handlers for 0xA, 0x32, 0x40 trap types
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmb * and "ta 3" and "ta 4".
25cf1a301a396c38e8adf52c15f537b80d2483f7jl case sizeof (int):
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Set the magic constants of the implementation.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl static struct {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "l1-dcache-line-size", &dcache_linesize, OPL_DCACHE_LSIZE,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "l1-icache-line-size", &icache_linesize, OPL_ICACHE_LSIZE,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "l2-cache-line-size", &ecache_alignsize, OPL_ECACHE_LSIZE,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "l2-cache-associativity", &ecache_associativity, OPL_ECACHE_NWAY
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl i = 0; a = vac_size;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl while (a >>= 1)
e98fafb9956429b59c817d4fbd27720c73879203jl * Enable features for Jupiter-only domains.
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * Do not enable all-Jupiter features and do not turn on
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * the cpu_alljupiter flag.
e98fafb9956429b59c817d4fbd27720c73879203jl * Enable ima hwcap for Jupiter-only domains. DR will prevent
e98fafb9956429b59c817d4fbd27720c73879203jl * addition of Olympus-C to all-Jupiter domains to preserve ima
e98fafb9956429b59c817d4fbd27720c73879203jl * hwcap semantics.
2006426383b0c487ff71a6a98f7dbcdf19211854Sean McEnroe * Enable shared context support.
51f7a915ca9727aa4f82226c887a3bffba8a174ehyw * Quick and dirty way to redefine locally in
51f7a915ca9727aa4f82226c887a3bffba8a174ehyw * OPL the value of IDSR_BN_SETS to 31 instead
51f7a915ca9727aa4f82226c887a3bffba8a174ehyw * of the standard 32 value. This is to workaround
51f7a915ca9727aa4f82226c887a3bffba8a174ehyw * REV_B of Olympus_c processor's problem in handling
51f7a915ca9727aa4f82226c887a3bffba8a174ehyw * more than 31 xcall broadcast.
51f7a915ca9727aa4f82226c887a3bffba8a174ehyw#endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (i = 0; i < NCPU; i++)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (i = 0; i < NCPU; i++)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Ship only to the first (IDSR_BN_SETS) CPUs. If we
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * find we have shipped to more than (IDSR_BN_SETS)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CPUs, set "index" to the highest numbered CPU in
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the set so we can ship to other CPUs a bit later on.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (;;) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If there is a big jump between the current tick
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * count and lasttick, we have probably hit a break
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * point. Adjust endtick accordingly to avoid panic.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (i = 0; i < bn_sets; i++) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (i = 0; i < IDSR_BN_SETS; i++) {
227649d1f6dea9a591a585aa7423daf7e195f131hyw * Only proceed to send more xcalls if all the
227649d1f6dea9a591a585aa7423daf7e195f131hyw * cpus in the previous IDSR_BN_SETS were completed.
227649d1f6dea9a591a585aa7423daf7e195f131hyw#endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Sequence through and ship to the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * remainder of the CPUs in the system
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * (e.g. other than the first
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * (IDSR_BN_SETS)) in reverse order.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If we've processed all the CPUs,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * exit the loop now and save
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * instructions.
227649d1f6dea9a591a585aa7423daf7e195f131hyw#endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (n < 8192)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (n < 8192)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Cpu private initialization.
e98fafb9956429b59c817d4fbd27720c73879203jl if (!((IS_OLYMPUS_C(cpunodes[cp->cpu_id].implementation)) ||
e98fafb9956429b59c817d4fbd27720c73879203jl cmn_err(CE_PANIC, "CPU%d Impl %d: Only SPARC64-VI(I) is "
25cf1a301a396c38e8adf52c15f537b80d2483f7jl extern int at_flags;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Initialize Error log Scratch register for error handling.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Enable MMU translating multiple page sizes for
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * sITLB and sDTLB.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Setup chip-specific trap handlers.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl at_flags = EF_SPARC_32PLUS | EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Due to the number of entries in the fully-associative tlb
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * this may have to be tuned lower than in spitfire.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Block stores do not invalidate all pages of the d$, pagecopy
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * et. al. need virtual translations with virtual coloring taken
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * into consideration. prefetch/ldd will pollute the d$ on the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * load side.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pp_consistent_coloring = PPAGE_STORE_VCOLORING | PPAGE_LOADS_POLLUTE;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "sparcv9+vis2 sparcv9+vis sparcv9 "
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "sparcv8plus+vis2 sparcv8plus+vis sparcv8plus "
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "sparcv8 sparcv8-fsmuld sparcv7 sparc";
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * On SPARC64-VI, there's no hole in the virtual address space
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The kpm mapping window.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * kpm_size:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The size of a single kpm range.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The overall size will be: kpm_size * vac_colors.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * kpm_vbase:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The virtual start address of the kpm range within the kernel
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * virtual address space. kpm_vbase has to be kpm_size aligned.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl kpm_size = (size_t)(128ull * 1024 * 1024 * 1024 * 1024); /* 128TB */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The traptrace code uses either %tick or %stick for
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * timestamping. We have %stick so we can use it.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * SPARC64-VI has a performance counter overflow interrupt
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Declare that this architecture/cpu combination does not support
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Called by setcpudelay
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * For SPARC64-VI we want to use the system clock rate as
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the basis for low level timing, due to support of mixed
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * speed CPUs and power managment.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_PANIC, "setcpudelay: invalid system_clock_freq");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Note: A version of this function is used by the debugger via the KDI,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and must be kept in sync with this version. Any changes made to this
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * function to support new chips or to accomodate errata must also be included
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * in the KDI-specific version. See us3_kdi.c.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (;;) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If there is a big jump between the current tick
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * count and lasttick, we have probably hit a break
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * point. Adjust endtick accordingly to avoid panic.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (n < 8192)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * init_mmu_page_sizes is set to one after the bootup time initialization
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * valid value.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * mmu_disable_ism_large_pages and mmu_disable_large_pages are the mmu-specific
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * versions of disable_ism_large_pages and disable_large_pages, and feed back
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * into those two hat variables at hat initialization time.
ec25b48f5e0576a68280c5e549673a266f0be346susansstatic uint_t mmu_disable_ism_large_pages = ((1 << TTE64K) |
ec25b48f5e0576a68280c5e549673a266f0be346susansstatic uint_t mmu_disable_auto_data_large_pages = ((1 << TTE64K) |
ec25b48f5e0576a68280c5e549673a266f0be346susansstatic uint_t mmu_disable_auto_text_large_pages = ((1 << TTE64K) |
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Re-initialize mmu_page_sizes and friends, for SPARC64-VI mmu support.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Called during very early bootup from check_cpus_set().
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Can be called to verify that mmu_page_sizes are set up correctly.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Set Olympus defaults. We do not use the function parameter.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* SPARC64-VI worst case DTLB parameters */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define LOCKED_DTLB_ENTRIES 5 /* 2 user TSBs, 2 nucleus, + OBP */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define AVAIL_DTLB_ENTRIES (TOTAL_DTLB_ENTRIES - LOCKED_DTLB_ENTRIES)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The function returns the mmu-specific values for the
582cbfcb3667abdae9fb5898568aeefcd75c283cjimand * hat's disable_large_pages, disable_ism_large_pages, and
ec25b48f5e0576a68280c5e549673a266f0be346susans * disable_auto_data_large_pages and
ec25b48f5e0576a68280c5e549673a266f0be346susans * disable_text_data_large_pages variables.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * mmu_init_large_pages is called with the desired ism_pagesize parameter.
1426d65aa9264a283c76d271972aeb7f6a070be3sm * It may be called from set_platform_defaults, if some value other than 4M
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * is desired. mmu_ism_pagesize is the tunable. If it has a bad value,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * then only warn, since it would be bad form to panic due to a user typo.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The function re-initializes the mmu_disable_ism_large_pages variable.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_WARN, "Unrecognized mmu_ism_pagesize value 0x%lx",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Function to reprogram the TLBs when page sizes used
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * by a process change significantly.
1426d65aa9264a283c76d271972aeb7f6a070be3smstatic void
22a594afa42005018d3b4a567823c3370ed5f1fajimandmmu_setup_page_sizes(struct hat *hat, uint64_t *ttecnt, uint8_t *tmp_pgsz)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Don't program 2nd dtlb for kernel and ism hat
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * hat->sfmmu_pgsz[] is an array whose elements
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * contain a sorted order of page sizes. Element
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 0 is the most commonly used page size, followed
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * by element 1, and so on.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * ttecnt[] is an array of per-page-size page counts
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * mapped into the process.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If the HAT's choice for page sizes is unsuitable,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * we can override it here. The new values written
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * to the array will be handed back to us later to
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * do the actual programming of the TLB hardware.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This implements PAGESIZE programming of the sTLB
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * if large TTE counts don't exceed the thresholds.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* otherwise, accept what the HAT chose for us */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The HAT calls this function when an MMU context is allocated so that we
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * can reprogram the large TLBs appropriately for the new process using
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the context.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The caller must hold the HAT lock.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Don't program 2nd dtlb for kernel and ism hat
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If supported, reprogram the TLBs to a larger pagesize.
2006426383b0c487ff71a6a98f7dbcdf19211854Sean McEnroe new_cext = hat->sfmmu_scdp->scd_sfmmup->sfmmu_cext;
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah * assert cnum should be invalid, this is because pagesize
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah * can only be changed after a proc's ctxs are invalidated.
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah for (i = 0; i < max_mmu_ctxdoms; i++) {
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah#endif /* DEBUG */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * sfmmu_setctx_sec() will take care of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * rest of the dirty work for us.
22a594afa42005018d3b4a567823c3370ed5f1fajimand * This function assumes that there are either four or six supported page
22a594afa42005018d3b4a567823c3370ed5f1fajimand * sizes and at most two programmable TLBs, so we need to decide which
22a594afa42005018d3b4a567823c3370ed5f1fajimand * page sizes are most important and then adjust the TLB page sizes
22a594afa42005018d3b4a567823c3370ed5f1fajimand * accordingly (if supported).
22a594afa42005018d3b4a567823c3370ed5f1fajimand * If these assumptions change, this function will need to be
22a594afa42005018d3b4a567823c3370ed5f1fajimand * updated to support whatever the new limits are.
22a594afa42005018d3b4a567823c3370ed5f1fajimandmmu_check_page_sizes(sfmmu_t *sfmmup, uint64_t *ttecnt)
22a594afa42005018d3b4a567823c3370ed5f1fajimand * We only consider reprogramming the TLBs if one or more of
22a594afa42005018d3b4a567823c3370ed5f1fajimand * the two most used page sizes changes and we're using
22a594afa42005018d3b4a567823c3370ed5f1fajimand * large pages in this process.
22a594afa42005018d3b4a567823c3370ed5f1fajimand /* Sort page sizes. */
22a594afa42005018d3b4a567823c3370ed5f1fajimand for (i = 0; i < mmu_page_sizes; i++) {
22a594afa42005018d3b4a567823c3370ed5f1fajimand for (j = 0; j < mmu_page_sizes; j++) {
22a594afa42005018d3b4a567823c3370ed5f1fajimand oldval = sfmmup->sfmmu_pgsz[0] << 8 | sfmmup->sfmmu_pgsz[1];
22a594afa42005018d3b4a567823c3370ed5f1fajimand /* Check 2 largest values after the sort. */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Return processor specific async error structure
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * size used.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (sizeof (opl_async_flt_t));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The cpu_sync_log_err() function is called via the [uc]e_drain() function to
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * post-process CPU events that are dequeued. As such, it can be invoked
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * from softint context, from AST processing in the trap() flow, or from the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * panic flow. We decode the CPU-specific data, and take appropriate actions.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Historically this entry point was used to log the actual cmn_err(9F) text;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * now with FMA it is used to prepare 'flt' to be converted into an ereport.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * With FMA this function now also returns a flag which indicates to the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * caller whether the ereport should be posted (1) or suppressed (0).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * No extra processing of urgent error events.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Always generate ereports for these events.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Additional processing for synchronous errors.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The validity: SFSR_MK_UE bit has been checked
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * in opl_cpu_sync_error()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * No more check is required.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * opl_flt->flt_eid_mod and flt_eid_sid have been set by H/W,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and they have been retrieved in cpu_queue_events()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We want to skip logging only if ALL the following
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * conditions are true:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 1. We are not panicing already.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 2. The error is a memory error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 3. There is only one error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 4. The error is on a retired page.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 5. The error occurred under on_trap
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * protection AFLT_PROT_EC
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Do not log an error from
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the retired page
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * For the following error cases, the processor HW does
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * not set the flt_eid_mod/flt_eid_sid. Instead, SW will attempt
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * to assign appropriate values here to reflect what we
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * think is the most likely cause of the problem w.r.t to
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the particular error event. For Buserr and timeout
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * error event, we will assign OPL_ERRID_CHANNEL as the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * most likely reason. For TLB parity or multiple hit
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * error events, we will assign the reason as
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL_ERRID_CPU (cpu related problem) and set the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * flt_eid_sid to point to the cpuid.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * flt_eid_sid will not be used for this case.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * In case of no effective error bit
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (1);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Retire the bad page that may contain the flushed error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Invoked by error_init() early in startup and therefore before
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * startup_errorq() is called to drain any error Q -
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * startup()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * startup_end()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * error_init()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * cpu_error_init()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * errorq_init()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * errorq_drain()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * start_other_cpus()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The purpose of this routine is to create error-related taskqs. Taskqs
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * are used for this purpose because cpu_lock can't be grabbed from interrupt
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * context.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "is not page aligned");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We route all errors through a single switch statement.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_WARN, "discarding async error %p with invalid "
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Routine for panic hook callback from panic_idle().
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Nothing to do here.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Routine to return a string identifying the physical name
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * associated with a memory/cache error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_get_mem_unum(int synd_status, ushort_t flt_synd, uint64_t flt_stat,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * An AFSR of -1 defaults to a memory syndrome.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if ((ret = plat_get_mem_unum(synd_code, flt_addr, flt_bus_id,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Wrapper for cpu_get_mem_unum() routine that takes an
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * async_flt struct rather than explicit arguments.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_get_mem_unum_aflt(int synd_status, struct async_flt *aflt,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We always pass -1 so that cpu_get_mem_unum will interpret this as a
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * memory error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This routine is a more generic interface to cpu_get_mem_unum()
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * that may be used by other modules (e.g. mm).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Check for an invalid address.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ret = cpu_get_mem_unum(synd_status, (ushort_t)synd, *afsr, afar,
e98fafb9956429b59c817d4fbd27720c73879203jl CPU->cpu_id, flt_in_memory, flt_status, unum, UNUM_NAMLEN, lenp);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Routine to return memory information associated
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * with a physical address and syndrome.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep,
e98fafb9956429b59c817d4fbd27720c73879203jl return ((p2get_mem_info)(synd_code, afar, mem_sizep, seg_sizep,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Routine to return a string identifying the physical
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * name associated with a cpuid.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This routine exports the name buffer size.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Flush the entire ecache by ASI_L2_CNTL.U2_FLUSH
25cf1a301a396c38e8adf52c15f537b80d2483f7jl flush_ecache(ecache_flushaddr, cpunodes[CPU->cpu_id].ecache_size,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Encode the data saved in the opl_async_flt_t struct into
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the FM ereport payload.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_payload_add_aflt(struct async_flt *aflt, nvlist_t *payload,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_FLT_STATUS) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FLT_STATUS,
e98fafb9956429b59c817d4fbd27720c73879203jl (uint8_t *)&cpunodes[opl_flt->flt_eid_sid].version, sbuf);
e98fafb9956429b59c817d4fbd27720c73879203jl fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * No resource is created but the cpumem DE will find
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the defective path by retreiving EID from SFSR which is
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * included in the payload.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void) cpu_get_mem_unum_aflt(0, aflt, unum, UNUM_NAMLEN, &len);
e98fafb9956429b59c817d4fbd27720c73879203jl (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, NULL,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * No resource is created but the cpumem DE will find
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the defective path by retreiving EID from SFSR which is
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * included in the payload.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Returns whether fault address is valid for this error bit and
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * whether the address is "in memory" (i.e. pf_is_memory returns 1).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_flt_in_memory(opl_async_flt_t *opl_flt, uint64_t t_afsr_bit)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * In OPL SCF does the stick synchronization.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * In OPL SCF does the stick synchronization.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Cpu private unitialization. OPL cpus do not use the private area.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Always flush an entire cache.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Create the scheme "cpu" FMRI.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void) fm_fmri_cpu_set(detector, FM_CPU_SCHEME_VERSION, NULL,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl aflt->flt_inst, (uint8_t *)&cpunodes[aflt->flt_inst].version,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Encode all the common data into the ereport.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl fm_ena_generate(aflt->flt_id, FM_ENA_FMT1), detector, NULL);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Encode the error specific data that was saved in
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the async_flt structure into the ereport.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_run_bus_error_handlers(struct async_flt *aflt, int expected)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl status = ndi_fm_handler_dispatch(ddi_root_node(), NULL, &de);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if ((aflt->flt_prot == AFLT_PROT_NONE) && (status == DDI_FM_FATAL))
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_errorq_dispatch(char *error_class, void *payload, size_t payload_sz,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Set hw copy limits.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * /etc/system will be parsed later and can override one or more
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * of these settings.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * At this time, ecache size seems only mildly relevant.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We seem to run into issues with the d-cache and stalls
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * we see on misses.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Cycle measurement indicates that 2 byte aligned copies fare
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * little better than doing things with VIS at around 512 bytes.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 4 byte aligned shows promise until around 1024 bytes. 8 Byte
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * aligned is faster whenever the source and destination data
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * in cache and the total size is less than 2 Kbytes. The 2K
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * limit seems to be driven by the 2K write cache.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * When more than 2K of copies are done in non-VIS mode, stores
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * backup in the write cache. In VIS mode, the write cache is
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * bypassed, allowing faster cache-line writes aligned on cache
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * boundaries.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * In addition, in non-VIS mode, there is no prefetching, so
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * for larger copies, the advantage of prefetching to avoid even
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * occasional cache misses is enough to justify using the VIS code.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * During testing, it was discovered that netbench ran 3% slower
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * when hw_copy_limit_8 was 2K or larger. Apparently for server
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * applications, data is only used once (copied to the output
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * buffer, then copied by the network device off the system). Using
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the VIS copy saves more L2 cache state. Network copies are
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * around 1.3K to 1.5K in size for historical reasons.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Therefore, a limit of 1K bytes will be used for the 8 byte
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * aligned copy even for large caches and 8 MB ecache. The
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * infrastructure to allow different limits for different sized
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * caches is kept to allow further tuning in later releases.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * First time through - should be before /etc/system
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * is read.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Could skip the checks for zero but this lets us
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * preserve any debugger rewrites.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * MP initialization. Called *after* /etc/system has
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * been parsed. One CPU has already been initialized.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Need to cater for /etc/system having scragged one
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * of our values.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Same size ecache. We do nothing unless we
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * have a pessimistic ecache setting. In that
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * case we become more optimistic (if the cache is
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * large enough).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Need to adjust hw_copy_limit* from our
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pessimistic uniprocessor value to a more
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * optimistic UP value *iff* it hasn't been
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * A different ecache size. Can this even happen?
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The previous value that we set
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * is unchanged (i.e., it hasn't been
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * scragged by /etc/system). Rewrite it.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl watched = watch_disable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE);
b9a675d4c12d7767d04d2537f6e3b1083f56f291mb if (cpu[getprocessorid()] == &cpu0 && opl_cpu0_log_setup == 1) {
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmb * Support for "ta 3"
b9a675d4c12d7767d04d2537f6e3b1083f56f291mb * If we are being called at boot time on cpu0 the error
b9a675d4c12d7767d04d2537f6e3b1083f56f291mb * log is already set up in cpu_setup. Clear the
b9a675d4c12d7767d04d2537f6e3b1083f56f291mb * opl_cpu0_log_setup flag so that a subsequent DR of cpu0 will
b9a675d4c12d7767d04d2537f6e3b1083f56f291mb * do the proper initialization.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Initialize Error log Scratch register for error handling.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl this_cpu_log = va_to_pa((void*)(((uint64_t)opl_err_log) +
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Queue one event in ue_queue based on ecc_type_to_info entry.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_queue_one_event(opl_async_flt_t *opl_flt, char *reason,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl strlen(reason) + strlen(eccp->ec_reason) < MAX_REASON_STRING) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl aflt->flt_in_memory = cpu_flt_in_memory(opl_flt, opl_flt->flt_bit);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ASSERT(aflt->flt_status & (OPL_ECC_SYNC_TRAP|OPL_ECC_URGENT_TRAP));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Queue events on async event queue one event per error bit.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Return number of events queued.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_queue_events(opl_async_flt_t *opl_flt, char *reason, uint64_t t_afsr_errs)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Queue expected errors, error bit and fault type must must match
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * in the ecc_type_to_info table.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (eccp = ecc_type_to_info; t_afsr_errs != 0 && eccp->ec_desc != NULL;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * UE error event can be further
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * classified/breakdown into finer granularity
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * based on the flt_eid_mod value set by HW. We do
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * special handling here so that we can report UE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * error in finer granularity as ue_mem,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * ue_channel, ue_cpu or ue_path.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Need to advance eccp pointer by flt_eid_mod
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * so that we get an appropriate ecc pointer
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * EID # of advances
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * ----------------------------------
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL_ERRID_MEM 0
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL_ERRID_CHANNEL 1
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL_ERRID_CPU 2
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL_ERRID_PATH 3
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Sync. error wrapper functions.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We use these functions in order to transfer here from the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * nucleus trap handler information about trap type (data or
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * instruction) and trap level (0 or above 0). This way we
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * get rid of using SFSR's reserved bits.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlopl_cpu_isync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr)
25cf1a301a396c38e8adf52c15f537b80d2483f7jlopl_cpu_isync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr)
25cf1a301a396c38e8adf52c15f537b80d2483f7jlopl_cpu_dsync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr)
25cf1a301a396c38e8adf52c15f537b80d2483f7jlopl_cpu_dsync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The fj sync err handler transfers control here for UE, BERR, TO, TLB_MUL
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and TLB_PRT.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This function is designed based on cpu_deferred_error().
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jlopl_cpu_sync_error(struct regs *rp, ulong_t t_sfar, ulong_t t_sfsr,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We need to look at p_flag to determine if the thread detected an
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * error while dumping core. We can't grab p_lock here, but it's ok
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * because we just need a consistent snapshot and we know that everyone
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * else will store a consistent set of bits while holding p_lock. We
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * don't have to worry about a race because SDOCORE is set once prior
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * to doing i/o from the process's address space and is never cleared.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * handle the specific error
e98fafb9956429b59c817d4fbd27720c73879203jl aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate &
25cf1a301a396c38e8adf52c15f537b80d2483f7jl aflt->flt_panic = (uchar_t)(tl != 0 || aft_testfatal != 0 ||
25cf1a301a396c38e8adf52c15f537b80d2483f7jl aflt->flt_status = (derr) ? OPL_ECC_DSYNC_TRAP : OPL_ECC_ISYNC_TRAP;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If SFSR.FV is not set, both SFSR and SFAR/SFPAR values are uncertain.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * So, clear all error bits to avoid mis-handling and force the system
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * panicked.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We skip all the procedures below down to the panic message call.
e98fafb9956429b59c817d4fbd27720c73879203jl cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, (void *)&opl_flt,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If either UE and MK bit is off, this is not valid UE error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If it is not valid UE error, clear UE & MK_UE bits to prevent
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * mis-handling below.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * aflt->flt_stat keeps the original bits as a reference.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If the trap occurred in privileged mode at TL=0, we need to check to
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * see if we were executing in the kernel under on_trap() or t_lofault
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * protection. If so, modify the saved registers so that we return
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * from the trap to the appropriate trampoline routine.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * for peeks and caut_gets errors are expected
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If we're in user mode or we're doing a protected copy, we either
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * want the ASTON code below to send a signal to the user process
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * or we want to panic if aft_panic is set.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If we're in privileged mode and we're not doing a copy, then we
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * need to check if we've trampolined. If we haven't trampolined,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * we should panic.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl } else if (!trampolined) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If we've trampolined due to a privileged TO or BERR, or if an
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * unprivileged TO or BERR occurred, we don't want to enqueue an
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * event for that TO or BERR. Queue all other events (if any) besides
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * User mode, suppress messages if
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * cpu_berr_to_verbose is not set.
e98fafb9956429b59c817d4fbd27720c73879203jl if (((log_sfsr & SFSR_ERRS) && (cpu_queue_events(&opl_flt, pr_reason,
e98fafb9956429b59c817d4fbd27720c73879203jl cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, (void *)&opl_flt,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Panic here if aflt->flt_panic has been set. Enqueued errors will
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * be logged as part of the panic flow.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (pr_reason[0] == 0)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If we queued an error and we are going to return from the trap and
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * the error was in user mode or inside of a copy routine, set AST flag
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * so the queue will be drained before returning to user mode. The
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * AST processing will also act on our failure policy.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlopl_cpu_urgent_error(struct regs *rp, ulong_t p_ugesr, ulong_t tl)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* normalize tl */
e98fafb9956429b59c817d4fbd27720c73879203jl aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ?
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * HW does not set mod/sid in case of urgent error.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * So we have to set it here.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (cpu_queue_events(&opl_flt, pr_reason, p_ugesr) == 0) {
e98fafb9956429b59c817d4fbd27720c73879203jl cpu_errorq_dispatch(FM_EREPORT_CPU_INV_URG, (void *)&opl_flt,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Initialization error counters resetting.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic void
25cf1a301a396c38e8adf52c15f537b80d2483f7jlopl_ras_online(void *arg, cpu_t *cp, cyc_handler_t *hdlr, cyc_time_t *when)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl when->cyt_when = cp->cpu_id * (((hrtime_t)NANOSEC * 10)/ NCPU);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl when->cyt_interval = (hrtime_t)NANOSEC * opl_async_check_interval;
3cbfd4cf9e3b91b2efed73184d8c6dc586fc1935jimand /* do not reprogram stlb */
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand } else if (!plat_prom_preserve_kctx_is_supported()) {
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand /* OBP does not support non-zero primary context */
3cbfd4cf9e3b91b2efed73184d8c6dc586fc1935jimand kcontextreg = ((uint64_t)new_cext_nucleus << CTXREG_NEXT_SHIFT) |
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (lpsize == 0) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* no setting for segkmem_lpsize in /etc/system: use default */
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmb * Support for ta 3.
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmb * We allocate here a buffer for each cpu
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmb * for saving the current register window.
50eff7691a80815571befbb7c9fe5f0bbf22dcbdmbstatic void
b9a675d4c12d7767d04d2537f6e3b1083f56f291mb * opl_ta3 should only be called once at boot time.
b9a675d4c12d7767d04d2537f6e3b1083f56f291mb opl_ta3_save = (char *)kmem_alloc(NCPU * sizeof (win_regs_t),
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The following are functions that are unused in
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL cpu module. They are defined here to resolve
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * dependencies in the "unix" module.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Unused functions that should never be called in
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * OPL are coded with ASSERT(0).
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_check_ce(int flag, uint64_t pa, caddr_t va, uint_t psz)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_ce_count_unum(struct async_flt *ecc, int len, char *unum)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlcpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* ARGSUSED */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
f4b0f0a6df9b5e6b49e5fa30bd0a8c885a01e728hyw/*ARGSUSED*/
f4b0f0a6df9b5e6b49e5fa30bd0a8c885a01e728hywread_ecc_data(struct async_flt *aflt, short verbose, short ce_err)
f4b0f0a6df9b5e6b49e5fa30bd0a8c885a01e728hyw/*ARGSUSED*/
f4b0f0a6df9b5e6b49e5fa30bd0a8c885a01e728hywce_scrub_xdiag_recirc(struct async_flt *aflt, errorq_t *eqp,
f4b0f0a6df9b5e6b49e5fa30bd0a8c885a01e728hyw return (0);
f4b0f0a6df9b5e6b49e5fa30bd0a8c885a01e728hyw/*ARGSUSED*/
1ba18ff1efb9bb19540297cbee0a824685da1622jimand#define PROM_SPARC64VII_MODE_PROPNAME "SPARC64-VII-mode"
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * Check for existence of OPL OBP property that indicates
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * SPARC64-VII support. By default, only enable Jupiter
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * features if the property is present. It will be
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * present in all-Jupiter domains by OBP if the domain has
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * been selected by the user on the system controller to
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * run in Jupiter mode. Basically, this OBP property must
1ba18ff1efb9bb19540297cbee0a824685da1622jimand * be present to turn on the cpu_alljupiter flag.
1ba18ff1efb9bb19540297cbee0a824685da1622jimand return ((prom_getprop(prom_rootnode(), PROM_SPARC64VII_MODE_PROPNAME,
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand#define PROM_KCTX_PRESERVED_PROPNAME "context0-page-size-preserved"
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand * Check for existence of OPL OBP property that indicates support for
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand * preserving Solaris kernel page sizes when entering OBP. We need to
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand * check the prom tree since the ddi tree is not yet built when the
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand * platform startup sequence is called.
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand * Check for existence of context0-page-size-preserved property
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand * in virtual-memory prom node.
febcc4a52c3ed7fe3a106da2c2ba52c56afd5111jimand pnode = (pnode_t)prom_getphandle(prom_mmu_ihandle());