Searched defs:reg (Results 226 - 250 of 341) sorted by relevance

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/illumos-gate/usr/src/uts/common/io/i40e/
H A Di40e_main.c914 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, i40e->i40e_dip, 0, "reg",
1997 uint32_t reg; local
2009 reg = I40E_READ_REG(hw, I40E_PFINT_LNKLSTN(i - 1));
2010 VERIFY3U(reg, ==, I40E_QUEUE_TYPE_EOL);
2013 reg = I40E_READ_REG(hw, I40E_PFINT_LNKLST0);
2014 VERIFY3U(reg, ==, I40E_QUEUE_TYPE_EOL);
2025 reg = I40E_READ_REG(hw, I40E_QRX_ENA(i));
2026 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK))
2028 VERIFY((reg & I40E_QRX_ENA_QENA_REQ_MASK) ==
2030 reg
2047 uint32_t reg; local
2111 uint32_t reg; local
2239 uint32_t reg; local
2274 uint32_t j, reg; local
2378 uint32_t reg; local
2416 uint32_t j, reg; local
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/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_82599.c1684 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1685 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
2044 * @reg: analog register to read
2049 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) argument
2056 (reg << 8));
2068 * @reg: atlas register to write
2073 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) argument
2079 core_ctl = (reg << 8) | val;
H A Dixgbe_phy.c107 * @reg: I2C device register to read from
114 u16 reg, u16 *val, bool lock)
127 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
128 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
141 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
187 * @reg: I2C device register to read from
193 u16 reg, u16 *val)
195 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
202 * @reg: I2C device register to read from
209 u16 reg, u1
113 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val, bool lock) argument
192 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) argument
208 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) argument
224 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val, bool lock) argument
288 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) argument
304 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) argument
2735 u16 reg; local
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/illumos-gate/usr/src/boot/sys/i386/include/
H A Dcpufunc.h446 rxcr(u_int reg) argument
450 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
455 load_xcr(u_int reg, uint64_t val) argument
461 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
684 read_cyrix_reg(u_char reg) argument
686 outb(0x22, reg);
691 write_cyrix_reg(u_char reg, u_char data) argument
693 outb(0x22, reg);
774 u_char read_cyrix_reg(u_char reg);
783 void write_cyrix_reg(u_char reg, u_cha
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/illumos-gate/usr/src/uts/common/io/nvme/
H A Dnvme.c438 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val) argument
440 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
443 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
447 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val) argument
449 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
452 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
456 nvme_get64(nvme_t *nvme, uintptr_t reg) argument
460 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
463 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
469 nvme_get32(nvme_t *nvme, uintptr_t reg) argument
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/illumos-gate/usr/src/boot/sys/amd64/include/
H A Dcpufunc.h468 rxcr(u_int reg) argument
472 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
477 load_xcr(u_int reg, u_long val) argument
483 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
/illumos-gate/usr/src/boot/sys/boot/sparc64/loader/
H A Dmain.c410 u_long pstate, reg; local
416 reg = ldxa(TLB_DAR_SLOT(tlb_locked, i),
418 if (TLB_TAR_VA(reg) != va)
420 reg = dtlb_get_data_sun4u(tlb_locked, i);
422 reg >>= TD_PA_SHIFT;
425 return (reg & TD_PA_CH_MASK);
426 return (reg & TD_PA_SF_MASK);
435 u_long pstate, reg; local
441 reg = ldxa(TLB_DAR_SLOT(tlb_locked, i),
443 if (TLB_TAR_VA(reg) !
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/illumos-gate/usr/src/uts/common/io/axf/
H A Daxf_usbgem.c411 uint16_t reg; local
591 /* verify rxctrl reg */
914 DPRINTF(4, (CE_CONT, "!%s: %s called, reg:%x val:%x",
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_82575.c135 u32 reg = 0; local
143 reg = E1000_READ_REG(hw, E1000_MDIC);
144 ext_mdio = !!(reg & E1000_MDIC_DEST);
151 reg = E1000_READ_REG(hw, E1000_MDICNFG);
152 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
1296 u32 reg; local
1305 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1306 reg |= E1000_PCS_CFG_PCS_EN;
1307 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1310 reg
1394 u32 reg; local
1636 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; local
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H A De1000_phy.c3092 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) argument
3096 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3432 u16 reg = BM_PHY_REG_NUM(offset); local
3438 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3448 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3453 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3456 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3473 DEBUGOUT2("Could not access PHY reg
3536 u16 reg = BM_PHY_REG_NUM(offset); local
3645 u16 reg = BM_PHY_REG_NUM(offset); local
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/illumos-gate/usr/src/lib/libshell/common/sh/
H A Dxec.c273 static int p_switch(register struct regnod *reg) argument
276 while(reg)
278 n+=p_arg(reg->regptr,0);
279 n+=sh_tclear(reg->regcom);
280 reg = reg->regnxt;
1849 register struct argnod *rex=(struct argnod*)t->reg.regptr;
1866 do sh_exec(t->reg.regcom,(t->reg.regflag?0:flags));
1867 while(t->reg
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/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dtlan.c1173 * reg The register whose contents are to be
1185 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val) argument
1206 TLan_MiiSendData(BASE, reg, 5); /* Register # */
1334 * reg The register whose contents are to be
1345 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val) argument
1362 TLan_MiiSendData(BASE, reg, 5); /* Register # */
/illumos-gate/usr/src/cmd/fs.d/udfs/fstyp/
H A Dud_lib.c1496 make_regid(ud_handle_t h, struct regid *reg, char *id, int32_t type) argument
1498 reg->reg_flags = 0;
1499 (void) strncpy(reg->reg_id, id, 23);
1505 dis = (struct dom_id_suffix *)reg->reg_ids;
1513 uis = (struct udf_id_suffix *)reg->reg_ids;
1520 iis = (struct impl_id_suffix *)reg->reg_ids;
1527 print_regid(FILE *fout, char *name, struct regid *reg, int32_t type) argument
1530 name, reg->reg_flags, reg->reg_id);
1536 dis = (struct dom_id_suffix *)reg
1564 print_regid(FILE *fout, char *name, struct regid *reg) argument
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/illumos-gate/usr/src/uts/common/fs/udfs/
H A Dudf_subr.c905 ud_update_regid(struct regid *reg) argument
909 bzero(reg->reg_id, 23);
910 (void) strncpy(reg->reg_id, SUN_IMPL_ID, SUN_IMPL_ID_LEN);
911 reg->reg_ids[0] = SUN_OS_CLASS;
912 reg->reg_ids[1] = SUN_OS_ID;
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/
H A Dlm_vf.c217 u32_t reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + LM_FW_VF_QZONE_ID(vf_info,q_idx) * 4; local
219 REG_WR(PFDEV(pdev), reg, val); local
556 u32_t reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + LM_FW_VF_QZONE_ID(vf_info,q_idx) * 4; local
558 REG_WR(PFDEV(pdev), reg, val); local
3537 u32_t reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + LM_FW_VF_QZONE_ID(vf_info,q_idx) * 4; local
3539 REG_WR(PFDEV(pdev), reg, val); local
/illumos-gate/usr/src/uts/common/io/audio/ac97/
H A Dac97.c65 #define SHADOW(ac, reg) ((ac)->shadow[((reg) / sizeof (uint16_t))])
312 ac_probe_reg(ac97_t *ac, uint8_t reg) argument
318 val = RD(reg);
319 WR(reg, 0xffff);
320 if (RD(reg) != 0) {
324 WR(reg, val);
651 ac_wr(ac97_t *ac, uint8_t reg, uint16_t val) argument
653 if ((reg < LAST_SHADOW_REG) && (reg >
667 ac_rd(ac97_t *ac, uint8_t reg) argument
680 ac_set(ac97_t *ac, uint8_t reg, uint16_t val) argument
690 ac_clr(ac97_t *ac, uint8_t reg, uint16_t val) argument
827 ac_stereo_set(ac97_ctrl_t *ctrl, uint64_t value, uint8_t reg) argument
841 ac_mono_set(ac97_ctrl_t *ctrl, uint64_t value, uint8_t reg, int shift) argument
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/illumos-gate/usr/src/uts/common/io/audio/drv/audioemu10k/
H A Daudioemu10k.c217 emu10k_read_reg(emu10k_devc_t *devc, int reg, int chn) argument
224 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f);
227 if (reg & 0xff000000) {
228 size = (reg >> 24) & 0x3f;
229 offset = (reg >> 16) & 0x1f;
239 emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value) argument
246 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f);
248 if (reg & 0xff000000) {
249 size = (reg >> 24) & 0x3f;
250 offset = (reg >> 1
283 emu10k_write_efx(emu10k_devc_t *devc, int reg, unsigned int value) argument
1095 unsigned int reg; local
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/illumos-gate/usr/src/uts/common/io/audio/drv/audiopci/
H A Daudiopci.c762 audiopci_mono(audiopci_dev_t *dev, audiopci_ctrl_num_t num, uint8_t reg) argument
770 audiopci_ak_write(dev, reg, val);
774 audiopci_mono8(audiopci_dev_t *dev, audiopci_ctrl_num_t num, uint8_t reg) argument
782 audiopci_ak_write(dev, reg, val);
/illumos-gate/usr/src/uts/common/io/audio/drv/audiosolo/
H A Daudiosolo.c221 * solo_read access ext. regs via solo_cmd(0xc0, reg) followed by solo_get_byte
310 solo_write(solo_dev_t *dev, uint8_t reg, uint8_t val) argument
312 solo_cmd1(dev, reg, val);
316 solo_read(solo_dev_t *dev, uint8_t reg) argument
318 if (solo_cmd(dev, 0xc0) && solo_cmd(dev, reg)) {
/illumos-gate/usr/src/uts/common/io/bfe/
H A Dbfe.c311 bfe_wait_bit(bfe_t *bfe, uint32_t reg, uint32_t bit, argument
318 v = INL(bfe, reg);
340 bfe_read_phy(bfe_t *bfe, uint32_t reg) argument
346 (reg << BFE_MDIO_RA_SHIFT) |
355 bfe_write_phy(bfe_t *bfe, uint32_t reg, uint32_t val) argument
361 (reg << BFE_MDIO_RA_SHIFT) |
/illumos-gate/usr/src/uts/common/io/cxgbe/t4nex/
H A Dt4_nexus.c236 int rc, id, *reg; local
245 "reg", &reg, &n);
249 pf = PCI_REG_FUNC_G(reg[0]);
250 ddi_prop_free(reg);
985 DDI_PROP_DONTPASS, "reg", &data, &n);
988 "failed to lookup \"reg\" property: %d", rc);
/illumos-gate/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c106 uint16_t reg; member in struct:isa_node
788 pci_regspec_t *reg; local
875 * For each "reg" property with a length, allocate memory
879 DDI_PROP_DONTPASS, "reg", (caddr_t)&reg,
881 cardbus_err(dip, 1, "Failed to read reg property\n");
891 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
892 offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
893 switch (PCI_REG_ADDR_G(reg[
1002 pci_regspec_t *reg; local
1096 uint32_t reg[3], *breg; local
3069 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; local
3082 uint32_t reg[3]; local
3141 pci_regspec_t *reg; local
3347 pci_regspec_t *available, *reg; local
3506 pci_regspec_t *reg; local
[all...]
/illumos-gate/usr/src/uts/common/io/comstar/port/iscsit/
H A Discsit_isns.c69 * Flag for replace reg not set
296 isns_reg_type_t reg);
977 * registered to, then cause a re-reg attempt.
1544 isns_reg_type_t reg)
1551 switch (reg) {
1562 rc = isnst_register(svr, itarget, reg);
1566 rc = isnst_register(svr, NULL, reg);
1543 isnst_update_one_server(iscsit_isns_svr_t *svr, isns_target_t *itarget, isns_reg_type_t reg) argument
/illumos-gate/usr/src/uts/common/pcmcia/cs/
H A Dcs.c6690 uint32_t reg = crt->iobase0_p; local
6693 csx_Put8(cis_handle, reg, base & 0x0ff);
6694 reg = reg + 2;
/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_dbg.c113 ql_read_reg(qlge_t *qlge, uint32_t reg) argument
115 uint32_t data = ql_get32(qlge, reg);
124 ql_write_reg(qlge_t *qlge, uint32_t reg, uint32_t data) argument
126 ql_put32(qlge, reg, data);
142 * Wait up to "delay" seconds until the register "reg"'s
147 ql_wait_reg_bit(qlge_t *qlge, uint32_t reg, uint32_t wait_bit, int set, argument
164 reg_status = ql_read_reg(qlge, reg);
181 cmn_err(CE_WARN, "qlge(%d)wait reg %x, bit %x time out",
182 qlge->instance, reg, wait_bit);
960 struct ql_device_reg *reg; local
1824 ql_read_serdes_reg(qlge_t *qlge, uint32_t reg, uint32_t *data) argument
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