Lines Matching defs:reg
106 uint16_t reg;
788 pci_regspec_t *reg;
875 * For each "reg" property with a length, allocate memory
879 DDI_PROP_DONTPASS, "reg", (caddr_t)®,
881 cardbus_err(dip, 1, "Failed to read reg property\n");
891 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
892 offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
893 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
897 entry, reg[i].pci_size_low, &mem_answer);
910 reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer);
911 reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer);
918 entry, reg[i].pci_size_low, &mem_answer);
924 reg[i].pci_phys_low = (uint32_t)mem_answer;
925 reg[i].pci_phys_mid = 0;
955 entry, reg[i].pci_size_low, &io_answer);
960 reg[i].pci_phys_low = io_answer;
965 kmem_free(reg, length);
976 ®[i]) != PCICFG_SUCCESS) {
977 kmem_free(reg, length);
984 kmem_free(reg, length);
1002 pci_regspec_t *reg;
1026 * For each "reg" property with a length, allocate memory.
1029 DDI_PROP_DONTPASS, "reg", (caddr_t)®,
1031 cardbus_err(dip, 1, "Failed to read reg property\n");
1039 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
1040 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
1045 entry, reg[i].pci_size_low, &io_answer);
1048 reg[i].pci_phys_low = io_answer;
1051 range.par_phys_hi = reg[i].pci_phys_hi |
1053 range.par_phys_low = reg[i].pci_phys_low;
1054 range.par_phys_mid = reg[i].pci_phys_mid;
1055 range.rng_size = reg[i].pci_size_low;
1061 kmem_free(reg, length);
1068 kmem_free(reg, length);
1077 isa_phdl.io_decode_reg = 0x58; /* Pos decoded IO space 0 reg */
1096 uint32_t reg[3], *breg;
1110 if ((length / sizeof (reg)) < 1) {
1116 * Add the "reg" property.
1118 reg[0] = 0;
1119 reg[1] = breg[1] + phdl->io_base;
1120 reg[2] = breg[2];
1137 "reg", (int *)reg, 3);
1143 "cardbus_add_isa_reg: I/O decode reg (0x%x) set to 0x%x\n",
2053 * are stored in the reg structure of the bridge.
2070 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp,
2074 * does'nt have a "reg" property fail the
2085 * For each "reg" property with a length, add that to the
2739 * Add to the "reg" property
2843 * Add to the "reg" property.
2979 * Add to the "reg" property
3032 * Add to the "reg" property
3069 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0};
3071 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
3074 "reg", reg, 5));
3082 uint32_t reg[3];
3112 * Add the "reg" property.
3114 reg[0] = 0;
3115 reg[1] = node->reg;
3116 reg[2] = node->span;
3119 "basereg", (int *)reg, 3);
3141 pci_regspec_t *reg;
3154 dip, DDI_PROP_DONTPASS, "reg",
3155 (caddr_t)®, &rlen);
3158 "cardbus_config_setup, reg = 0x%p\n", (void *) reg);
3164 cardbus_err(dip, 1, "reg present, but unable to get memory\n");
3167 cardbus_err(dip, 1, "no reg property\n");
3183 kmem_free((caddr_t)reg, rlen);
3188 "reg", (int *)reg, 5)) != 0) {
3190 "Failed to update reg property, error code %d\n", ret);
3191 kmem_free((caddr_t)reg, rlen);
3205 PCI_REG_BUS_G(reg->pci_phys_hi),
3206 PCI_REG_DEV_G(reg->pci_phys_hi),
3207 PCI_REG_FUNC_G(reg->pci_phys_hi));
3208 kmem_free((caddr_t)reg, rlen);
3214 PCI_REG_BUS_G(reg->pci_phys_hi),
3215 PCI_REG_DEV_G(reg->pci_phys_hi),
3216 PCI_REG_FUNC_G(reg->pci_phys_hi),
3217 reg->pci_phys_hi, (void *) cfgaddr);
3241 PCI_REG_BUS_G(reg->pci_phys_hi),
3242 PCI_REG_DEV_G(reg->pci_phys_hi),
3243 PCI_REG_FUNC_G(reg->pci_phys_hi));
3248 kmem_free((caddr_t)reg, rlen);
3347 pci_regspec_t *available, *reg;
3355 "reg", (caddr_t)®, &rlen);
3361 cardbus_err(dip, 1, "reg present, but unable to get memory\n");
3364 cardbus_err(dip, 1, "no reg property\n");
3375 kmem_free((caddr_t)reg, rlen);
3392 PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
3393 PCI_REG_DEV_G(reg->pci_phys_hi),
3394 PCI_REG_FUNC_G(reg->pci_phys_hi), 0);
3418 kmem_free((caddr_t)reg, rlen);
3462 * Allocate memory for the existing reg(s) plus one and then
3506 pci_regspec_t *reg;
3514 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen);
3520 cardbus_err(dip, 1, "reg present, but unable to get memory\n");
3523 cardbus_err(dip, 1, "no reg property\n");
3528 * Allocate memory for the existing reg(s) plus one and then
3536 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
3537 PCI_REG_DEV_G(reg->pci_phys_hi),
3538 PCI_REG_FUNC_G(reg->pci_phys_hi),
3575 bcopy(reg, newreg, rlen);
3579 * Write out the new "reg" property
3582 dip, "reg", (int *)newreg,
3585 kmem_free((caddr_t)reg, rlen);
4501 "cardbus_dump_reg: \"reg\" has %d elements\n", nelems);