dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * CDDL HEADER START
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * The contents of this file are subject to the terms of the
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Common Development and Distribution License (the "License").
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * You may not use this file except in compliance with the License.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * See the License for the specific language governing permissions
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * and limitations under the License.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * When distributing Covered Code, include this CDDL HEADER in each
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * If applicable, add the following below this CDDL HEADER, with the
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * fields enclosed by brackets "[]" replaced with your own identifying
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dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * CDDL HEADER END
7a0c1e298cab158fe4113f2e75e46140eb4825e9Crisson Guanghao Hu * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Broadcom BCM4401 chipsets use two rings :
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * - One TX : For sending packets down the wire.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * - One RX : For receving packets.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Each ring can have any number of descriptors (configured during attach).
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * As of now we configure only 128 descriptor per ring (TX/RX). Each descriptor
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * has address (desc_addr) and control (desc_ctl) which holds a DMA buffer for
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * the packet and control information (like start/end of frame or end of table).
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * The descriptor table is allocated first and then a DMA buffer (for a packet)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * is allocated and linked to each descriptor.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Each descriptor entry is bfe_desc_t structure in bfe. During TX/RX
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * interrupt, the stat register will point to current descriptor being
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Here's an example of TX and RX ring :
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Base of the descriptor table is programmed using BFE_DMATX_CTRL control
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * register. Each 'addr' points to DMA buffer (or packet data buffer) to
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * be transmitted and 'ctl' has the length of the packet (usually MTU).
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | addr |Descriptor 0 |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | addr |Descriptor 1 | SOF (start of the frame)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | ... |Descriptor... | EOF (end of the frame)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | addr |Descritor 127 |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | ctl | EOT | EOT (End of Table)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * 'r_curr_desc' : pointer to current descriptor which can be used to transmit
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * 'r_avail_desc' : decremented whenever a packet is being sent.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * 'r_cons_desc' : incremented whenever a packet is sent down the wire and
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * notified by an interrupt to bfe driver.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Base of the descriptor table is programmed using BFE_DMARX_CTRL control
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * register. Each 'addr' points to DMA buffer (or packet data buffer). 'ctl'
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * contains the size of the DMA buffer and all the DMA buffers are
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * pre-allocated during attach and hence the maxmium size of the packet is
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * also known (r_buf_len from the bfe_rint_t structure). During RX interrupt
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * the packet length is embedded in bfe_header_t which is added by the
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * chip in the beginning of the packet.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | addr |Descriptor 0 |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | addr |Descriptor 1 |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | ... |Descriptor... |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | addr |Descriptor 127|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * | ctl | EOT | EOT (End of Table)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ----------------------|
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * 'r_curr_desc' : pointer to current descriptor while receving a packet.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Used for checking PHY (link state, speed)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra#define BFE_TIMEOUT_INTERVAL (1000 * 1000 * 1000)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Chip restart action and reason for restart
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra#define BFE_ACTION_RESTART 0x1 /* For restarting the chip */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra#define BFE_ACTION_RESTART_SETPROP 0x2 /* restart due to setprop */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra#define BFE_ACTION_RESTART_FAULT 0x4 /* restart due to fault */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra#define BFE_ACTION_RESTART_PKT 0x8 /* restart due to pkt timeout */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrastatic char bfe_ident[] = "bfe driver for Broadcom BCM4401 chipsets";
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Function Prototypes for bfe driver.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrastatic void bfe_error(dev_info_t *, char *, ...);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrastatic int bfe_mac_getprop(void *, const char *, mac_prop_id_t, uint_t,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrastatic int bfe_mac_setprop(void *, const char *, mac_prop_id_t, uint_t,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra const void *);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misraint bfe_mac_set_ether_addr(void *, const uint8_t *);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Macros for ddi_dma_sync().
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Supported Broadcom BCM4401 Cards.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * DMA attributes for device registers, packet data (buffer) and
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * descriptor table.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrastatic struct ddi_device_acc_attr bfe_dev_attr = {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrastatic struct ddi_device_acc_attr bfe_buf_attr = {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0, /* dma_attr_addr_lo */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0, /* dma_attr_burstsizes */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0 /* dma_attr_flags */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0, /* dma_attr_addr_lo */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0, /* dma_attr_burstsizes */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0 /* dma_attr_flags */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Ethernet broadcast addresses.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ASSERT(mutex_owned(&bfe->bfe_tx_ring.r_lock)); \
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Debugging and error reproting code.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ddi_driver_name(dip), ddi_get_instance(dip), buf);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Grabs all necessary locks to block any other operation on the chip.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Grab all the locks.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * - bfe_rwlock : locks down whole chip including RX.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * - tx's r_lock : locks down only TX side.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Note that we don't use RX's r_lock.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Release lock on chip/drver.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Release all the locks in the order in which they were grabbed.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * It's used to make sure that the write to device register was successful.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_wait_bit(bfe_t *bfe, uint32_t reg, uint32_t bit,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < t; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* if device still didn't see the value */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * PHY functions (read, write, stop, reset and startup)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) bfe_wait_bit(bfe, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 10, 0);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra return ((INL(bfe, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_write_phy(bfe_t *bfe, uint32_t reg, uint32_t val)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) bfe_wait_bit(bfe, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 10, 0);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * It resets the PHY layer.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_RESET);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < 10; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (i == 10) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "Timeout waiting for PHY to reset");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Make sure timer function is out of our way and especially during
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Stops the PHY
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_PWRDN |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Report the link status to MAC layer.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * This timeout function fires at BFE_TIMEOUT_INTERVAL to check the link
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We don't grab any lock because bfe can't go away.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * untimeout() will wait for this timeout instance to complete.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe->bfe_chip_action & BFE_ACTION_RESTART) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Restart the chip.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_chip_action &= ~BFE_ACTION_RESTART_FAULT;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_chip_action &= ~BFE_ACTION_RESTART_PKT;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Restart will register a new timeout */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE2(chip__restart, int, bfe->bfe_unit,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra char *, "pkt timeout");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (BFE_ACTION_RESTART | BFE_ACTION_RESTART_PKT);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Report the link status to MAC layer if link status changed.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe->bfe_chip.duplex == LINK_DUPLEX_FULL) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Starts PHY layer.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra MII_ABILITY_100BASE_TX_FD | MII_ABILITY_100BASE_TX |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra MII_ABILITY_10BASE_T_FD | MII_ABILITY_10BASE_T);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Supported hardware modes are in bmsr.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Assume no capabilities are supported in the hardware.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Assume property is set.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (!(bfe->bfe_chip_action & BFE_ACTION_RESTART_SETPROP)) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Property is not set which means bfe_mac_setprop()
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * is not called on us.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (s == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (s == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (s == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (s == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (s == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (s == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (s == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra "No valid link mode selected. Powering down PHY");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * If property is set then user would have goofed up. So we
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * go back to default properties.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_chip_action &= ~BFE_ACTION_RESTART_SETPROP;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe->bfe_adv_aneg && (bmsr & MII_STATUS_CANAUTONEG)) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_periodic_id = ddi_periodic_add(bfe_timeout,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void *)bfe, BFE_TIMEOUT_INTERVAL, DDI_IPL_0);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE1(first__timeout, int, bfe->bfe_unit);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE4(phy_started, int, bfe->bfe_unit,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Reports link status back to MAC Layer.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra mac_link_update(bfe->bfe_machdl, bfe->bfe_chip.link);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Reads PHY/MII registers and get the link status for us.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_mii_exp = bfe_read_phy(bfe, MII_AN_EXPANSION);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * If exp register is not present in PHY.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Forced mode */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra } else if ((!(bmsr & MII_STATUS_CANAUTONEG)) ||
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra } else if (anar & anlpar & MII_ABILITY_100BASE_TX_FD) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra } else if (anar & anlpar & MII_ABILITY_100BASE_T4) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra } else if (anar & anlpar & MII_ABILITY_100BASE_TX) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra } else if (anar & anlpar & MII_ABILITY_10BASE_T_FD) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra } else if (anar & anlpar & MII_ABILITY_10BASE_T) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * If speed or link status or duplex mode changed then report to
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * MAC layer which is done by the caller.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_cam_write(bfe_t *bfe, uchar_t *d, int index)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) bfe_wait_bit(bfe, BFE_CAM_CTRL, BFE_CAM_BUSY, 10, 1);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Chip related functions (halt, reset, start).
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Disables interrupts.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Wait until TX and RX finish their job.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) bfe_wait_bit(bfe, BFE_ENET_CTRL, BFE_ENET_DISABLE, 20, 1);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Disables DMA engine.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE2(chip__restart, int, bfe->bfe_unit,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Halt chip and PHY.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Init variables.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Reset chip and start PHY.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * DMA descriptor rings.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Disables core by stopping the clock.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) bfe_wait_bit(bfe, BFE_SBTMSLOW, BFE_REJECT, 100, 0);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) bfe_wait_bit(bfe, BFE_SBTMSHIGH, BFE_BUSY, 100, 1);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | BFE_RESET));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Resets core.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * First disable the core.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Change bar0 window to map sbtopci registers.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bar_orig = pci_config_get32(bfe->bfe_conf_handle, BFE_BAR0_WIN);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra pci_config_put32(bfe->bfe_conf_handle, BFE_BAR0_WIN, BFE_REG_PCI);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Just read it and don't do anything */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Restore bar0 window mapping.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra pci_config_put32(bfe->bfe_conf_handle, BFE_BAR0_WIN, bar_orig);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Resets chip and starts PHY.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Set the interrupt vector for the enet core */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* check if core is up */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (INL(bfe, BFE_DMARX_STAT) & BFE_STAT_EMASK) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) bfe_wait_bit(bfe, BFE_DMARX_STAT, BFE_STAT_SIDLE,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL_OR(bfe, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_RXMAXLEN, bfe->bfe_rx_ring.r_buf_len);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_TXMAXLEN, bfe->bfe_tx_ring.r_buf_len);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Program DMA channels */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * DMA addresses need to be added to BFE_PCI_DMA
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_tx_ring.r_desc_cookie.dmac_laddress + BFE_PCI_DMA);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_rx_ring.r_desc_cookie.dmac_laddress + BFE_PCI_DMA);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * It enables interrupts. Should be the last step while starting chip.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Enable the chip and core */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Enable interrupts */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Common code to take care of setting RX side mode (filter).
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ether_addr_t mac[ETHERADDRL] = {0, 0, 0, 0, 0, 0};
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We don't touch RX filter if we were asked to suspend. It's fine
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * if chip is not active (no interface is plumbed on us).
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe->bfe_chip_state == BFE_CHIP_SUSPENDED)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if ((bfe->bfe_chip_mode & BFE_RX_MODE_ENABLE) == 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra } else if (bfe->bfe_chip_mode & BFE_RX_MODE_PROMISC) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Flush everything */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Disable CAM */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We receive all multicast packets.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < BFE_MAX_MULTICAST_TABLE - 1; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Enable CAM */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE2(rx__mode__filter, int, bfe->bfe_unit,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Reset various variable values to initial state.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Initial assumption */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Initializes TX side descriptor entries (bfe_desc_t). Each descriptor entry
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * has control (desc_ctl) and address (desc_addr) member.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < r->r_ndesc; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[i].desc_ctl),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * DMA addresses need to be added to BFE_PCI_DMA
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[i].desc_addr),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (r->r_buf_dma[i].cookie.dmac_laddress + BFE_PCI_DMA));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = GET_DESC(r, (uint32_t *)&(r->r_desc[i - 1].desc_ctl));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[i - 1].desc_ctl),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) SYNC_DESC(r, 0, r->r_ndesc, DDI_DMA_SYNC_FORDEV);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Initializes RX side descriptor entries (bfe_desc_t). Each descriptor entry
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * has control (desc_ctl) and address (desc_addr) member.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < r->r_ndesc; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[i].desc_ctl),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[i].desc_addr),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (r->r_buf_dma[i].cookie.dmac_laddress + BFE_PCI_DMA));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Initialize rx header (len, flags) */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bzero(r->r_buf_dma[i].addr, sizeof (bfe_rx_header_t));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) SYNC_BUF(r, i, 0, sizeof (bfe_rx_header_t),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = GET_DESC(r, (uint32_t *)&(r->r_desc[i - 1].desc_ctl));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[i - 1].desc_ctl),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) SYNC_DESC(r, 0, r->r_ndesc, DDI_DMA_SYNC_FORDEV);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* TAIL of RX Descriptor */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(r->r_bfe, BFE_DMARX_PTR, ((i) * sizeof (bfe_desc_t)));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Stop the chip first & then Reset the chip. At last enable interrupts.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Reset chip and start PHY.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Initailize Descriptor Rings.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Check link, speed and duplex mode */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Clear chip statistics.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Stat registers are cleared by reading.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (r = BFE_TX_GOOD_O; r <= BFE_TX_PAUSE; r += 4)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (r = BFE_RX_GOOD_O; r <= BFE_RX_NPAUSE; r += 4)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Collect chip statistics.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (r = BFE_TX_GOOD_O; r <= BFE_TX_PAUSE; r += 4) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (r = BFE_RX_GOOD_O; r <= BFE_RX_NPAUSE; r += 4) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_good_octets, tx_good_pkts, tx_octets
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_pkts, tx_broadcast_pkts, tx_multicast_pkts
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_len_64, tx_len_65_to_127, tx_len_128_to_255
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_underruns, tx_total_cols, tx_single_cols
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_multiple_cols, tx_excessive_cols, tx_late_cols
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * tx_defered, tx_carrier_lost, tx_pause_pkts
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_good_octets, rx_good_pkts, rx_octets
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_pkts, rx_broadcast_pkts, rx_multicast_pkts
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_len_64, rx_len_65_to_127, rx_len_128_to_255
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_missed_pkts, rx_crc_align_errs, rx_undersize
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_crc_errs, rx_align_errs, rx_symbol_errs
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * rx_pause_pkts, rx_nonpause_pkts
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* txerr += bfe->bfe_hw_stats.tx_carrier_lost; */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_stats.ether_stat_tx_late_collisions +=
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_stats.ether_stat_macrcv_errors += rxerr;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_stats.ether_stat_macxmt_errors += txerr;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Gets the state for dladm command and all.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_mac_getstat(void *arg, uint_t stat, uint64_t *val)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * MAC layer will ask for IFSPEED first and hence we
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * collect it only once.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Update stats from the hardware.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anar & MII_ABILITY_100BASE_TX_FD) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anar & MII_ABILITY_100BASE_TX) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anar & MII_ABILITY_10BASE_T_FD) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anar & MII_ABILITY_10BASE_T) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anar & MII_ABILITY_PAUSE) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anar & MII_AN_ADVERT_REMFAULT) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASE_T4) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASEX_FD) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASEX) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_bmsr & MII_STATUS_10_FD) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = ((bfe->bfe_mii_bmsr & MII_STATUS_CANAUTONEG) != 0);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_bmsr & MII_STATUS_REMFAULT) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = bfe->bfe_stats.ether_stat_first_collisions;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_bmcr & MII_CONTROL_ANE) != 0 &&
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_T4) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_TX_FD) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_TX) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anlpar & MII_ABILITY_10BASE_T_FD) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anlpar & MII_ABILITY_10BASE_T) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_exp & MII_AN_EXP_LPCANAN) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anlpar & MII_ABILITY_PAUSE) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (bfe->bfe_mii_anlpar & MII_STATUS_REMFAULT) != 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = bfe->bfe_stats.ether_stat_multi_collisions;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = bfe->bfe_stats.ether_stat_tooshort_errors;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = bfe->bfe_stats.ether_stat_tx_late_collisions;
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyerbfe_mac_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz,
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer bcopy(&bfe->bfe_chip.duplex, val, sizeof (link_duplex_t));
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer bcopy(&bfe->bfe_chip.speed, val, sizeof (uint64_t));
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyerbfe_mac_propinfo(void *arg, const char *name, mac_prop_id_t num,
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_aneg);
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_100fdx);
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_100hdx);
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_10fdx);
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_10hdx);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_mac_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra const void *val)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_chip_action = BFE_ACTION_RESTART_SETPROP;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We need to stop the timer before grabbing locks
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * otherwise we can land-up in deadlock with untimeout.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We leave SETPROP because properties can be
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_chip_action &= ~(BFE_ACTION_RESTART);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* kick-off a potential stopped downstream */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_mac_set_ether_addr(void *arg, const uint8_t *ea)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We need to stop the timer before grabbing locks otherwise
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * we can land-up in deadlock with untimeout.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * First halt the chip by disabling interrupts.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * This will leave the PHY running.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Disable RX register.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Send a packet down the wire.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * There is a big reason why we don't check for '0'. It becomes easy
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * for us to not roll over the ring since we are based on producer (tx)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * and consumer (reclaim by an interrupt) model. Especially when we
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * run out of TX descriptor, chip will send a single interrupt and
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * both producer and consumer counter will be same. So we keep a
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * difference of 1 always.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Get the DMA buffer to hold packet.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Gather statistics.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bcmp(buf, bfe_broadcast, ETHERADDRL) != 0)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Program the DMA descriptor (start and end of frame are same).
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra v = (pktlen & BFE_DESC_LEN) | BFE_DESC_IOC | BFE_DESC_SOF |
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[cur].desc_ctl), v);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * DMA addresses need to be added to BFE_PCI_DMA
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[cur].desc_addr),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (r->r_buf_dma[cur].cookie.dmac_laddress + BFE_PCI_DMA));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Sync the packet data for the device.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) SYNC_BUF(r, cur, 0, pktlen, DDI_DMA_SYNC_FORDEV);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Move to next descriptor slot */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) SYNC_DESC(r, 0, r->r_ndesc, DDI_DMA_SYNC_FORDEV);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * The order should be 1,2,3,... for BFE_DMATX_PTR if 0,1,2,3,...
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * descriptor slot are being programmed.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra OUTL(bfe, BFE_DMATX_PTR, next * sizeof (bfe_desc_t));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Let timeout know that it must reset the chip if a
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * packet is not sent down the wire for more than 5 seconds.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_tx_stall_time = gethrtime() + (5 * 1000000000ULL);
954c6b5ec18168de579023aa3735121108026e9bSaurabh Misra DTRACE_PROBE1(tx__chip__not__active, int, bfe->bfe_unit);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe_send_a_packet(bfe, mp) == BFE_FAILURE) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_mac_set_promisc(void *arg, boolean_t promiscflag)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Set Promiscous on */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_mac_set_multicast(void *arg, boolean_t add, const uint8_t *macaddr)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * It was too much of pain to implement multicast in CAM. Instead
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * we never disable multicast filter.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_mac_set_promisc, /* sets promisc mode for snoop */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_mac_set_multicast, /* multicast implementation */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_mac_set_ether_addr, /* sets ethernet address (unicast) */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_mac_transmit_packet, /* transmits packet */
954c6b5ec18168de579023aa3735121108026e9bSaurabh Misra (BFE_ACTION_RESTART | BFE_ACTION_RESTART_FAULT);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Descriptor Protocol Error */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra "Descriptor Protocol Error. Halting Chip");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (BFE_ACTION_RESTART | BFE_ACTION_RESTART_FAULT);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Descriptor Error */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "Descriptor Error. Restarting Chip");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Receive Descr. Underflow */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra "Receive Descriptor Underflow. Restarting Chip");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (BFE_ACTION_RESTART | BFE_ACTION_RESTART_FAULT);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Error while sending a packet */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra "Error while sending a packet. Restarting Chip");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Error while receiving a packet */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra "Error while receiving a packet. Restarting Chip");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (BFE_ACTION_RESTART | BFE_ACTION_RESTART_FAULT);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * It will recycle a RX descriptor slot.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_rx_desc_buf_reinit(bfe_t *bfe, uint_t slot)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bzero(r->r_buf_dma[slot].addr, sizeof (bfe_rx_header_t));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) SYNC_BUF(r, slot, 0, BFE_RX_OFFSET, DDI_DMA_SYNC_FORDEV);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[slot].desc_ctl), v);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * DMA addresses need to be added to BFE_PCI_DMA
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[slot].desc_addr),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (r->r_buf_dma[slot].cookie.dmac_laddress + BFE_PCI_DMA));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Gets called from interrupt context to handle RX interrupt.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra current = (rxstat & BFE_STAT_CDMASK) / sizeof (bfe_desc_t);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Sync the buffer associated with the descriptor table entry.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We do this to make sure we are endian neutral. Chip is
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * big endian.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * The header looks like :-
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Offset 0 -> uint16_t len
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Offset 2 -> uint16_t flags
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Offset 4 -> uint16_t pad[12]
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Don't receive this packet if pkt length is greater than
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * MTU + VLAN_TAGSZ.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Recycle slot for later use */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if ((mp = allocb(len + VLAN_TAGSZ, BPRI_MED)) != NULL) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* sizeof (bfe_rx_header_t) + 2 */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Number of packets received so far */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Total bytes of packets received so far */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bcmp(mp->b_rptr, bfe_broadcast, ETHERADDRL) == 0)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Recycle the slot for later use */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Reinitialize the current descriptor slot's buffer so that
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * it can be reused.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) SYNC_DESC(r, 0, r->r_ndesc, DDI_DMA_SYNC_FORDEV);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra cur = INL(r->r_bfe, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Start with the last descriptor consumed by the chip.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE3(tx__reclaim, int, r->r_bfe->bfe_unit,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * There will be at least one descriptor to process.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[start].desc_ctl), v);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PUT_DESC(r, (uint32_t *)&(r->r_desc[start].desc_addr),
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (r->r_buf_dma[start].cookie.dmac_laddress + BFE_PCI_DMA));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Move to next descriptor in TX ring */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra r->r_cons_desc = start; /* consumed pointer */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * ISR for interrupt handling
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Grab the lock to avoid stopping the chip while this interrupt
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * is handled.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * It's necessary to read intr stat again because masking interrupt
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * register does not really mask interrupts coming from the chip.
954c6b5ec18168de579023aa3735121108026e9bSaurabh Misra DTRACE_PROBE2(bfe__interrupt, int, bfe->bfe_unit,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * If chip is suspended then we just return.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe->bfe_chip_state == BFE_CHIP_SUSPENDED) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE1(interrupt__chip__is__suspend, int,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Halt the chip again i.e basically disable interrupts.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DTRACE_PROBE1(interrupt__chip__not__active, int,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* A packet was received */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* A packet was sent down the wire */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* There was an error */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Pass the list of packets received from chip to MAC layer.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Let the MAC start sending pkts to a potential stopped stream.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Removes registered interrupt handler.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) ddi_intr_remove_handler(bfe->bfe_intrhdl);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Add an interrupt for the driver.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ret = ddi_intr_alloc(bfe->bfe_dip, &bfe->bfe_intrhdl,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0, /* inumber */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "ddi_intr_alloc() failed"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ret = ddi_intr_add_handler(bfe->bfe_intrhdl, bfe_interrupt, bfe, NULL);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "ddi_intr_add_handler() failed");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ret = ddi_intr_get_pri(bfe->bfe_intrhdl, &bfe->bfe_intrpri);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "ddi_intr_get_pri() failed");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Identify chipset family.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra vid = pci_config_get16(bfe->bfe_conf_handle, PCI_CONF_VENID);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra did = pci_config_get16(bfe->bfe_conf_handle, PCI_CONF_DEVID);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < (sizeof (bfe_cards) / sizeof (bfe_cards_t)); i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "bfe driver is attaching to unknown pci%d,%d"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Maps device registers.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ret = ddi_regs_map_setup(dip, 1, &bfe->bfe_mem_regset.addr, 0, 0,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "ddi_regs_map_setup failed");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Read EEPROM in prom[]
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < BFE_EEPROM_SIZE; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra prom[i] = INL(bfe, BFE_EEPROM_BASE + i * sizeof (uint32_t));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_dev_addr[0] = bfe->bfe_ether_addr[0] =
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_dev_addr[1] = bfe->bfe_ether_addr[1] =
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_dev_addr[2] = bfe->bfe_ether_addr[2] =
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_dev_addr[3] = bfe->bfe_ether_addr[3] =
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_dev_addr[4] = bfe->bfe_ether_addr[4] =
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_dev_addr[5] = bfe->bfe_ether_addr[5] =
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Ring Management routines
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_ring_buf_alloc(bfe_t *bfe, bfe_ring_t *r, int slot, int d)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra " alloc_handle failed");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra err = ddi_dma_mem_alloc(r->r_buf_dma[slot].handle,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra r->r_buf_len, &bfe_buf_attr, DDI_DMA_STREAMING,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra DDI_DMA_SLEEP, NULL, &r->r_buf_dma[slot].addr,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra err = ddi_dma_addr_bind_handle(r->r_buf_dma[slot].handle,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra " bind_handle failed");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra " more than one DMA cookie");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) ddi_dma_unbind_handle(r->r_buf_dma[slot].handle);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ddi_dma_free_handle(&r->r_buf_dma[slot].handle);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) ddi_dma_unbind_handle(r->r_buf_dma[slot].handle);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ddi_dma_free_handle(&r->r_buf_dma[slot].handle);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < r->r_ndesc; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra (void) ddi_dma_unbind_handle(r->r_desc_dma_handle);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra kmem_free(r->r_buf_dma, r->r_ndesc * sizeof (bfe_dma_t));
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_ring_desc_alloc(bfe_t *bfe, bfe_ring_t *r, int d)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra size_t size_krnl = 0, size_dma = 0, ring_len = 0;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra r->r_buf_dma = kmem_zalloc(size_krnl, KM_SLEEP);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra err = ddi_dma_alloc_handle(bfe->bfe_dip, &bfe_dma_attr_desc,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "bfe_ring_desc_alloc() failed on"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra " ddi_dma_alloc_handle()");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "bfe_ring_desc_alloc() failed on"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra " ddi_dma_mem_alloc()");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra err = ddi_dma_addr_bind_handle(r->r_desc_dma_handle,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(bfe->bfe_dip, "bfe_ring_desc_alloc() failed on"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra " ddi_dma_addr_bind_handle()");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We don't want to have multiple cookies. Descriptor should be
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * aligned to PAGESIZE boundary.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* The actual descriptor for the ring */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* For each descriptor, allocate a DMA buffer */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra for (i = 0; i < r->r_ndesc; i++) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe_ring_buf_alloc(bfe, r, i, d) != DDI_SUCCESS) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra while (i-- >= 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* We don't need the descriptor anymore */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra mutex_init(&bfe->bfe_tx_ring.r_lock, NULL, MUTEX_DRIVER, NULL);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_tx_ring.r_lockp = &bfe->bfe_tx_ring.r_lock;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_tx_ring.r_buf_len = BFE_MTU + sizeof (struct ether_header) +
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra mutex_init(&bfe->bfe_rx_ring.r_lock, NULL, MUTEX_DRIVER, NULL);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_rx_ring.r_lockp = &bfe->bfe_rx_ring.r_lock;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_rx_ring.r_buf_len = BFE_MTU + sizeof (struct ether_header) +
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Allocate TX Ring */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe_ring_desc_alloc(bfe, &bfe->bfe_tx_ring,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Allocate RX Ring */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe_ring_desc_alloc(bfe, &bfe->bfe_rx_ring,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra cmn_err(CE_NOTE, "RX ring allocation failed");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_tx_ring.r_flags = BFE_RING_ALLOCATED;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe->bfe_rx_ring.r_flags = BFE_RING_ALLOCATED;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if ((bfe = ddi_get_driver_private(dip)) == NULL) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(dip, "Unexpected error (no driver private data)"
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra " while resume");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Grab all the locks first.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* PHY will also start running */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (pci_config_setup(dip, &bfe->bfe_conf_handle) != DDI_SUCCESS) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Enable IO space, Bus Master and Memory Space accessess.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra ret = pci_config_get16(bfe->bfe_conf_handle, PCI_CONF_COMM);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra pci_config_put16(bfe->bfe_conf_handle, PCI_CONF_COMM,
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME | ret);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Identify hardware */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe_identify_hardware(bfe) == BFE_FAILURE) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(dip, "Could not map device registers");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Register with MAC layer
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if ((macreg = mac_alloc(MAC_VERSION)) == NULL) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra macreg->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if ((ret = mac_register(macreg, &bfe->bfe_machdl)) != 0) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(dip, "mac_register() failed with %d error", ret);
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra bfe_error(dip, "Could not allocate TX/RX Ring");
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Init and then reset the chip */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* PHY will also start running */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Even though we enable the interrupts here but chip's interrupt
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * is not enabled yet. It will be enabled once we plumb the interface.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (ddi_intr_enable(bfe->bfe_intrhdl) != DDI_SUCCESS) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misrabfe_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We need to stop the timer before grabbing locks otherwise
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * we can land-up in deadlock with untimeout.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * First unregister with MAC layer before stopping DMA
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (mac_unregister(bfe->bfe_machdl) != DDI_SUCCESS)
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Quiesce the chip first.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra /* Make sure timer is gone. */
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Free the DMA resources for buffer and then descriptors
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe->bfe_tx_ring.r_flags == BFE_RING_ALLOCATED) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra if (bfe->bfe_rx_ring.r_flags == BFE_RING_ALLOCATED) {
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * We need to stop the timer before grabbing locks otherwise
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * we can land-up in deadlock with untimeout.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Grab all the locks first.
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra * Quiesce the card for fast reboot
dd52495f0d9ba8ff6d84921ec0500be837896554Saurabh Misra 0, /* devo_refcnt */