Searched defs:patch_code (Results 1 - 7 of 7) sorted by relevance

/openjdk7/hotspot/src/share/vm/c1/
H A Dc1_LIRAssembler.cpp55 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) { argument
60 patch->install(_masm, patch_code, obj, info);
277 (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none)) {
498 assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
502 op->patch_code(), op->info(), op->pop_fpu_stack(),
796 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) { argument
799 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
802 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
805 reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide, unaligned);
811 assert(patch_code
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H A Dc1_CodeStubs.hpp384 void install(MacroAssembler* masm, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) { argument
394 switch (patch_code) {
532 G1PreBarrierStub(LIR_Opr addr, LIR_Opr pre_val, LIR_PatchCode patch_code, CodeEmitInfo* info) : argument
534 _patch_code(patch_code), _info(info)
551 LIR_PatchCode patch_code() const { return _patch_code; } function in class:G1PreBarrierStub
H A Dc1_LIR.cpp1178 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { argument
1184 patch_code,
1189 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { argument
1195 patch_code,
1199 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { argument
1205 patch_code,
1217 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { argument
1223 patch_code,
1228 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { argument
1234 patch_code,
1239 store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) argument
1250 volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) argument
1261 volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) argument
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H A Dc1_LIRGenerator.cpp1750 LIR_PatchCode patch_code = needs_patching ? lir_patch_normal : lir_patch_none; local
1751 __ store(value.result(), address, info, patch_code);
1816 LIR_PatchCode patch_code = needs_patching ? lir_patch_normal : lir_patch_none; local
1817 __ load(address, reg, info, patch_code);
H A Dc1_LIR.hpp1314 LIR_PatchCode patch_code() const { return _patch; } function in class:LIR_Op1
1998 void volatile_move(LIR_Opr src, LIR_Opr dst, BasicType type, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none) { append(new LIR_Op1(lir_move, src, dst, type, patch_code, info, lir_move_volatile)); }
2073 void volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none);
2074 void volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code);
2076 void load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none);
2080 void store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none);
2081 void store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code = lir_patch_none);
2082 void store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none);
2083 void volatile_store_mem_reg(LIR_Opr src, LIR_Address* address, CodeEmitInfo* info, LIR_PatchCode patch_code
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/openjdk7/hotspot/src/cpu/sparc/vm/
H A Dc1_LIRAssembler_sparc.cpp98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
1167 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { argument
1177 assert(patch_code == lir_patch_none, "no patching handled here");
1222 if (patch_code == lir_patch_none) {
1347 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1355 bool needs_patching = (patch_code != lir_patch_none);
1365 patch_code == lir_patch_none ||
1366 patch_code == lir_patch_normal, "patching doesn't match register");
1400 patching_epilog(patch, patch_code, src, info);
1494 LIR_PatchCode patch_code, CodeEmitInf
1346 mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) argument
1493 reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool unaligned) argument
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/openjdk7/hotspot/src/cpu/x86/vm/
H A Dc1_LIRAssembler_x86.cpp634 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { argument
641 assert(patch_code == lir_patch_none, "no patching handled here");
647 assert(patch_code == lir_patch_none, "no patching handled here");
653 assert(patch_code == lir_patch_none, "no patching handled here");
664 if (patch_code != lir_patch_none) {
974 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { argument
989 if (patch_code != lir_patch_none) {
1054 patch_code = lir_patch_low;
1063 patch_code = lir_patch_high;
1092 if (patch_code !
1174 mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool ) argument
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