/*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "c1/c1_Compilation.hpp"
#include "c1/c1_Instruction.hpp"
#include "c1/c1_InstructionPrinter.hpp"
#include "c1/c1_LIRAssembler.hpp"
#include "c1/c1_MacroAssembler.hpp"
#include "c1/c1_ValueStack.hpp"
#include "ci/ciInstance.hpp"
#ifdef TARGET_ARCH_x86
# include "nativeInst_x86.hpp"
# include "vmreg_x86.inline.hpp"
#endif
#ifdef TARGET_ARCH_sparc
# include "nativeInst_sparc.hpp"
# include "vmreg_sparc.inline.hpp"
#endif
#ifdef TARGET_ARCH_zero
# include "nativeInst_zero.hpp"
# include "vmreg_zero.inline.hpp"
#endif
#ifdef TARGET_ARCH_arm
# include "nativeInst_arm.hpp"
# include "vmreg_arm.inline.hpp"
#endif
#ifdef TARGET_ARCH_ppc
# include "nativeInst_ppc.hpp"
# include "vmreg_ppc.inline.hpp"
#endif
void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
// we must have enough patching space so that call can be inserted
}
#ifdef ASSERT
switch (code) {
case Bytecodes::_putstatic:
case Bytecodes::_getstatic:
break;
default:
}
switch (code) {
case Bytecodes::_putstatic:
case Bytecodes::_getstatic:
case Bytecodes::_anewarray:
case Bytecodes::_multianewarray:
case Bytecodes::_instanceof:
case Bytecodes::_checkcast:
break;
default:
}
} else {
}
#endif
}
//---------------------------------------------------------------
_compilation(c)
, _frame_map(c->frame_map())
{
_slow_case_stubs = new CodeStubList();
}
LIR_Assembler::~LIR_Assembler() {
}
}
BAILOUT("CodeBuffer overflow");
}
}
}
#ifndef PRODUCT
if (CommentedAssembly) {
s->print_name(&st);
}
#endif
s->emit_code(this);
#ifdef ASSERT
s->assert_no_unbound_labels();
#endif
}
}
}
}
}
}
handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch");
// entry code not emitted yet
if (CommentedAssembly) {
}
} else {
}
}
}
}
}
if (PrintLIR) {
}
for (int i = 0; i < n; i++) {
}
}
}
// if this block is the start of an exception handler, record the
// PC offset of the first instruction for later construction of
// the ExceptionHandlerTable
}
#ifndef PRODUCT
if (PrintLIRWithAssembly) {
// don't print Phi's
InstructionPrinter ip(false);
}
#endif /* PRODUCT */
#ifndef PRODUCT
if (CommentedAssembly) {
}
#endif
}
for (int i = 0; i < n; i++) {
#ifndef PRODUCT
if (CommentedAssembly) {
// Don't record out every op since that's too verbose. Print
// branches since they include block and stub names. Also print
// patching moves since they generate funny looking code.
}
}
if (PrintLIRWithAssembly) {
// print out the LIR operation followed by the resulting assembly
}
#endif /* PRODUCT */
}
#ifndef PRODUCT
if (PrintLIRWithAssembly) {
}
#endif /* PRODUCT */
}
}
#ifdef ASSERT
assert(false, "unbound label");
}
}
}
#endif
//----------------------------------debug info--------------------------------
}
}
}
}
return ins->state_before();
}
if (_pending_non_safepoint == src) {
return;
}
if (_pending_non_safepoint != NULL) {
// Got some old debug info. Get rid of it.
return;
}
if (_pending_non_safepoint_offset < pc_offset) {
}
}
// Remember the debug info.
}
}
// Index caller states in s, where 0 is the oldest, 1 its callee, etc.
// Return NULL if n is too large.
// Returns the caller_bci for the next-younger state, also.
ValueStack* t = s;
for (int i = 0; i < n; i++) {
if (t == NULL) break;
t = t->caller_state();
}
for (;;) {
t = tc;
s = s->caller_state();
}
}
// Visit scopes from oldest to youngest.
for (int n = 0; ; n++) {
if (s == NULL) break;
//Always pass false for reexecute since these ScopeDescs are never used for deopt
}
}
}
}
}
}
}
// must align calls sites, otherwise they can't be updated atomically on MP hardware
}
// emit the static call stub stuff out of line
case lir_static_call:
case lir_dynamic_call:
break;
case lir_optvirtual_call:
break;
case lir_icvirtual_call:
break;
case lir_virtual_call:
break;
default:
break;
}
// JSR 292
// Record if this method has MethodHandle invokes.
if (op->is_method_handle_invoke()) {
compilation()->set_has_method_handle_invokes(true);
}
// C2 leave fpu stack dirty clean it
if (UseSSE < 2) {
int i;
for ( i = 1; i <= 7 ; i++ ) {
ffree(i);
}
ffree(0);
}
}
#endif // X86 && TIERED
}
}
case lir_move:
} else {
}
break;
case lir_prefetchr:
break;
case lir_prefetchw:
break;
case lir_roundfp: {
break;
}
case lir_return:
break;
case lir_safepoint:
}
break;
case lir_fxch:
break;
case lir_fld:
break;
case lir_ffree:
break;
case lir_branch:
break;
case lir_push:
break;
case lir_pop:
break;
case lir_neg:
break;
case lir_leal:
break;
case lir_null_check:
if (GenerateCompilerNullChecks) {
} else {
}
}
break;
case lir_monaddr:
break;
#ifdef SPARC
case lir_pack64:
break;
case lir_unpack64:
break;
#endif
case lir_unwind:
break;
default:
break;
}
}
case lir_word_align: {
while (code_offset() % BytesPerWord != 0) {
}
break;
}
case lir_nop:
break;
case lir_label:
break;
case lir_build_frame:
build_frame();
break;
case lir_std_entry:
// init offsets
check_icache();
}
_masm->verified_entry();
build_frame();
break;
case lir_osr_entry:
osr_entry();
break;
case lir_24bit_FPU:
break;
case lir_reset_FPU:
reset_FPU();
break;
case lir_breakpoint:
breakpoint();
break;
case lir_fpop_raw:
fpop();
break;
case lir_membar:
membar();
break;
case lir_membar_acquire:
break;
case lir_membar_release:
break;
case lir_membar_loadload:
break;
case lir_membar_storestore:
break;
case lir_membar_loadstore:
break;
case lir_membar_storeload:
break;
case lir_get_thread:
break;
default:
break;
}
}
case lir_cmp:
"shouldn't be codeemitinfo for non-address operands");
}
break;
case lir_cmp_l2i:
case lir_cmp_fd2i:
case lir_ucmp_fd2i:
break;
case lir_cmove:
break;
case lir_shl:
case lir_shr:
case lir_ushr:
} else {
}
break;
case lir_add:
case lir_sub:
case lir_mul:
case lir_mul_strictfp:
case lir_div:
case lir_div_strictfp:
case lir_rem:
op->result_opr(),
break;
case lir_abs:
case lir_sqrt:
case lir_sin:
case lir_tan:
case lir_cos:
case lir_log:
case lir_log10:
case lir_exp:
case lir_pow:
break;
case lir_logic_and:
case lir_logic_or:
case lir_logic_xor:
op->result_opr());
break;
case lir_throw:
break;
case lir_xadd:
case lir_xchg:
break;
default:
break;
}
}
}
"round_fp: rounds register -> stack location");
}
void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) {
if (src->is_register()) {
if (dest->is_register()) {
} else if (dest->is_address()) {
} else {
}
if (dest->is_register()) {
} else {
}
} else if (src->is_constant()) {
if (dest->is_register()) {
} else if (dest->is_address()) {
} else {
}
} else if (src->is_address()) {
} else {
}
}
#ifndef PRODUCT
if (VerifyOopMaps || VerifyOops) {
bool v = VerifyOops;
VerifyOops = true;
while (!s.is_done()) {
OopMapValue v = s.current();
if (v.is_oop()) {
if (!r->is_stack()) {
#ifdef SPARC
#else
#endif
} else {
}
}
s.next();
}
VerifyOops = v;
}
#endif
}