1472N/A * or visit www.oracle.com if you need additional information or have any
1879N/A#ifndef SHARE_VM_C1_C1_LIR_HPP
1879N/A#include "c1/c1_ValueType.hpp"
3932N/A#include "oops/methodOop.hpp"
0N/Aclass BlockBegin;
0N/Aclass LIR_Assembler;
0N/Aclass CodeEmitInfo;
0N/Aclass CodeStubList;
0N/Aclass ArrayCopyStub;
0N/Aclass LIR_OpVisitState;
0N/Aclass FpuStackSim;
0N/Aclass LIR_OprDesc;
0N/Aclass LIR_OprPtr;
0N/Aclass LIR_Address;
0N/Aclass LIR_OprVisitor;
0N/A void type_check(BasicType t1, BasicType t2) const { assert(type() == t1 || type() == t2, "type check"); }
1297N/A void type_check(BasicType t1, BasicType t2, BasicType t3) const { assert(type() == t1 || type() == t2 || type() == t3, "type check"); }
1297N/A LIR_Const(jint i, bool is_address=false) { _value.set_type(is_address?T_ADDRESS:T_INT); _value.set_jint(i); }
1297N/A jint as_jint_bits() const { type_check(T_FLOAT, T_INT, T_ADDRESS); return _value.get_jint(); }
0N/A return as_jint_lo();
0N/A return as_jint_hi();
0N/A friend class LIR_OprFact;
0N/A , is_fpu_stack_offset_bits = 1 // used in assertion checking on x86 for FPU stack slot allocation
0N/A , is_fpu_stack_offset_mask = right_n_bits(is_fpu_stack_offset_bits) << is_fpu_stack_offset_shift
0N/A OprType type_field_valid() const { assert(is_register() || is_stack(), "should not be called otherwise"); return (OprType)(value() & type_mask); }
0N/A OprType type_field() const { return is_illegal() ? unknown_type : (OprType)(value() & type_mask); }
0N/A return double_size;
0N/A return single_size;
304N/A return single_size;
0N/A if (is_pointer()) {
0N/A bool is_float_kind() const { return is_pointer() ? pointer()->is_float_kind() : (kind_field() == fpu_register); }
0N/A bool is_single_stack() const { validate_type(); return check_value_mask(kind_mask | size_mask, stack_value | single_size); }
0N/A bool is_double_stack() const { validate_type(); return check_value_mask(kind_mask | size_mask, stack_value | double_size); }
0N/A bool is_cpu_register() const { validate_type(); return check_value_mask(kind_mask, cpu_register); }
0N/A bool is_virtual_cpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, cpu_register | virtual_mask); }
0N/A bool is_fixed_cpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, cpu_register); }
0N/A bool is_single_cpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, cpu_register | single_size); }
0N/A bool is_double_cpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, cpu_register | double_size); }
0N/A bool is_fpu_register() const { validate_type(); return check_value_mask(kind_mask, fpu_register); }
0N/A bool is_virtual_fpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, fpu_register | virtual_mask); }
0N/A bool is_fixed_fpu() const { validate_type(); return check_value_mask(kind_mask | virtual_mask, fpu_register); }
0N/A bool is_single_fpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, fpu_register | single_size); }
0N/A bool is_double_fpu() const { validate_type(); return check_value_mask(kind_mask | size_mask, fpu_register | double_size); }
0N/A bool is_xmm_register() const { validate_type(); return check_value_mask(kind_mask | is_xmm_mask, fpu_register | is_xmm_mask); }
0N/A bool is_single_xmm() const { validate_type(); return check_value_mask(kind_mask | size_mask | is_xmm_mask, fpu_register | single_size | is_xmm_mask); }
0N/A bool is_double_xmm() const { validate_type(); return check_value_mask(kind_mask | size_mask | is_xmm_mask, fpu_register | double_size | is_xmm_mask); }
0N/A bool is_single_word() const { assert(is_register() || is_stack(), "type check"); return check_value_mask(size_mask, single_size); }
0N/A bool is_double_word() const { assert(is_register() || is_stack(), "type check"); return check_value_mask(size_mask, double_size); }
0N/A bool is_virtual_register() const { assert(is_register(), "type check"); return check_value_mask(virtual_mask, virtual_mask); }
0N/A bool is_oop_register() const { assert(is_register() || is_stack(), "type check"); return type_field_valid() == object_type; }
0N/A BasicType type_register() const { assert(is_register() || is_stack(), "type check"); return as_BasicType(type_field_valid()); }
0N/A bool is_last_use() const { assert(is_register(), "only works for registers"); return (value() & last_use_mask) != 0; }
0N/A bool is_fpu_stack_offset() const { assert(is_register(), "only works for registers"); return (value() & is_fpu_stack_offset_mask) != 0; }
0N/A LIR_Opr make_last_use() { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | last_use_mask); }
0N/A LIR_Opr make_fpu_stack_offset() { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | is_fpu_stack_offset_mask); }
0N/A int single_stack_ix() const { assert(is_single_stack() && !is_virtual(), "type check"); return (int)data(); }
0N/A int double_stack_ix() const { assert(is_double_stack() && !is_virtual(), "type check"); return (int)data(); }
0N/A RegNr cpu_regnr() const { assert(is_single_cpu() && !is_virtual(), "type check"); return (RegNr)data(); }
0N/A RegNr cpu_regnrLo() const { assert(is_double_cpu() && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); }
0N/A RegNr cpu_regnrHi() const { assert(is_double_cpu() && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); }
0N/A RegNr fpu_regnr() const { assert(is_single_fpu() && !is_virtual(), "type check"); return (RegNr)data(); }
0N/A RegNr fpu_regnrLo() const { assert(is_double_fpu() && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); }
0N/A RegNr fpu_regnrHi() const { assert(is_double_fpu() && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); }
0N/A RegNr xmm_regnr() const { assert(is_single_xmm() && !is_virtual(), "type check"); return (RegNr)data(); }
0N/A RegNr xmm_regnrLo() const { assert(is_double_xmm() && !is_virtual(), "type check"); return (RegNr)lo_reg_half(); }
0N/A RegNr xmm_regnrHi() const { assert(is_double_xmm() && !is_virtual(), "type check"); return (RegNr)hi_reg_half(); }
0N/A if (is_double_cpu()) {
0N/A return as_register_lo();
0N/A return as_register();
0N/A friend class LIR_OpVisitState;
0N/A bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
304N/A static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
1601N/A static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
1601N/A static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
1601N/A static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }
304N/A static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
304N/A static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
304N/A static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
304N/A static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
1601N/A static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
1601N/A static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) |
1601N/A#ifdef __SOFTFP__
1601N/A#ifdef __SOFTFP__
304N/A ((type == T_FLOAT || type == T_DOUBLE) ? LIR_OprDesc::fpu_register : LIR_OprDesc::cpu_register) |
0N/Aclass LIR_OpLabel;
0N/Aclass LIR_OpBranch;
0N/Aclass LIR_OpConvert;
0N/Aclass LIR_OpAllocObj;
0N/Aclass LIR_OpRoundFP;
0N/Aclass LIR_OpDelay;
0N/Aclass LIR_OpAllocArray;
0N/Aclass LIR_OpCall;
0N/Aclass LIR_OpJavaCall;
0N/Aclass LIR_OpRTCall;
0N/Aclass LIR_OpArrayCopy;
0N/Aclass LIR_OpLock;
0N/Aclass LIR_OpTypeCheck;
0N/Aclass LIR_OpCompareAndSwap;
0N/Aclass LIR_OpProfileCall;