/vbox/include/VBox/vmm/ |
H A D | cpumctx-v1_6.h | 57 uint32_t pGdt; member in struct:VBOXGDTR_VER1_6
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/vbox/src/VBox/VMM/VMMR3/ |
H A D | SELM.cpp | 172 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX; 581 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered) 584 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt); 587 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX; 812 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC)); 825 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC); 850 AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc)); 985 if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt 988 Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt [all...] |
H A D | CPUM.cpp | 223 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt), 362 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt), 499 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt), 1529 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel); 1542 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel); 1580 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl, 1607 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
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H A D | CPUMDbg.cpp | 198 pValue->dtr.u64Base = pGdtr->pGdt; 1201 CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1329 CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
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H A D | PATMSSM.cpp | 1211 else if (offCpumCtx == (unsigned)RT_OFFSETOF(CPUMCTX_VER1_6, gdtr.pGdt)) 1213 LogFlow(("Changing pGdt offset from %x to %x\n", offCpumCtx, RT_OFFSETOF(CPUMCTX, gdtr.pGdt))); 1214 *pFixup = pVM->patm.s.pCPUMCtxGC + RT_OFFSETOF(CPUMCTX, gdtr.pGdt);
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H A D | PATMPatch.cpp | 1475 offset_base = RT_OFFSETOF(CPUMCTX, gdtr.pGdt);
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/vbox/src/VBox/VMM/VMMRC/ |
H A D | SELMRC.cpp | 84 int rc = MMGCRamRead(pVM, &Desc, (uint8_t *)(uintptr_t)GdtrGuest.pGdt + offEntry, sizeof(X86DESC)); 87 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, (uintptr_t)GdtrGuest.pGdt + offEntry, sizeof(X86DESC));
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/vbox/src/VBox/VMM/VMMAll/ |
H A D | TRPMAll.cpp | 588 Assert(gdtr.pGdt && gdtr.cbGdt > GuestIdte.Gen.u16SegSel); 590 if (!gdtr.pGdt) 593 pGdtEntry = gdtr.pGdt + (GuestIdte.Gen.u16SegSel >> X86_SEL_SHIFT) * sizeof(X86DESC);
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H A D | CPUMAllRegs.cpp | 193 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr; 517 return pVCpu->cpum.s.Hyper.gdtr.pGdt; 595 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
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H A D | SELMAll.cpp | 567 selLoadHiddenSelectorRegFromGuestTable(pVCpu, pCtx, pSReg, pCtx->gdtr.pGdt + (Sel & X86_SEL_MASK), Sel, iSReg);
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H A D | IEMAll.cpp | 2523 pCtx->gdtr.pGdt + (pCtx->tr.Sel & X86_SEL_MASK), IEM_ACCESS_SYS_RW); 2526 Log(("iemTaskSwitch: Failed to read new TSS descriptor in GDT. enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n", 2527 enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VAL(rcStrict))); 2535 Log(("iemTaskSwitch: Failed to commit new TSS descriptor in GDT. enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n", 2536 enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VAL(rcStrict))); 2732 pCtx->gdtr.pGdt + (SelTSS & X86_SEL_MASK), IEM_ACCESS_SYS_RW); 2735 Log(("iemTaskSwitch: Failed to read new TSS descriptor in GDT (2). enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n", 2736 enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VAL(rcStrict))); 2749 Log(("iemTaskSwitch: Failed to commit new TSS descriptor in GDT (2). enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n", 2750 enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VA [all...] |
H A D | IEMAllCImpl.cpp.h | 4166 GCPtrBase = pCtx->gdtr.pGdt; 4392 pCtx->gdtr.pGdt = GCPtrBase; 4416 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pIemCpu, pCtx->gdtr.cbGdt, pCtx->gdtr.pGdt, iEffSeg, GCPtrEffDst, enmEffOpSize); 4693 rcStrict = iemMemMap(pIemCpu, &pvDesc, 8, UINT8_MAX, pCtx->gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL), IEM_ACCESS_DATA_RW);
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H A D | EMAll.cpp | 666 CHECK_FIELD(gdtr.pGdt);
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/vbox/include/VBox/ |
H A D | types.h | 766 uint64_t pGdt; member in struct:VBOXGDTR
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/vbox/src/VBox/VMM/testcase/ |
H A D | tstVMStructSize.cpp | 302 CHECK_MEMBER_ALIGNMENT(CPUMCTX, gdtr.pGdt, 8);
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/vbox/src/recompiler/ |
H A D | VBoxRecompiler.c | 1432 pCtx->gdtr.pGdt = env->gdt.base; 2312 pVM->rem.s.Env.gdt.base = pCtx->gdtr.pGdt; 2636 if (pCtx->gdtr.pGdt != pVM->rem.s.Env.gdt.base) 2638 pCtx->gdtr.pGdt = pVM->rem.s.Env.gdt.base; 2890 if (pCtx->gdtr.pGdt != (RTGCPTR)pVM->rem.s.Env.gdt.base) 2892 pCtx->gdtr.pGdt = (RTGCPTR)pVM->rem.s.Env.gdt.base;
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/vbox/src/VBox/VMM/VMMR0/ |
H A D | HMR0.cpp | 1941 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags, 1968 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
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H A D | HMVMXR0.cpp | 3022 Gdtr.pGdt = (uintptr_t)Gdtr64.uAddr; 3030 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt); AssertRCReturn(rc, rc); 3074 PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK)); 4675 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pMixedCtx->gdtr.pGdt); AssertRCReturn(rc, rc); 4681 Log4(("Load[%RU32]: VMX_VMCS_GUEST_GDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->gdtr.pGdt)); 5080 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 5088 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 5096 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 5104 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 5112 pDesc = (PCX86DESCHC)(HostGdtr.pGdt [all...] |
H A D | HMR0A.asm | 298 add rax, qword [rsi + VMXRESTOREHOST.HostGdtr + 2] ; xAX <- descriptor offset + GDTR.pGdt.
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H A D | HMSVMR0.cpp | 1351 pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt; 2027 pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
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/vbox/include/iprt/ |
H A D | asm-amd64-x86.h | 130 uintptr_t pGdt; member in struct:RTGDTR
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