/* $Id$ */
/** @file
* EM - Execution Monitor(/Manager) - All contexts
*/
/*
* Copyright (C) 2006-2014 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#ifdef VBOX_WITH_IEM
#endif
#include "EMInternal.h"
#include <VBox/disopcode.h>
#ifndef IN_RC
#endif
#ifdef VBOX_WITH_IEM
//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
//# define VBOX_SAME_AS_EM
//# define VBOX_COMPARE_IEM_LAST
#endif
#ifdef VBOX_WITH_RAW_RING1
# define EM_EMULATE_SMSW
#endif
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** @def EM_ASSERT_FAULT_RETURN
* Safety check.
*
* Could in theory misfire on a cross page boundary access...
*
* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
* turns up an alias page instead of the original faulting one and annoying the
* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
*/
#if 0
#else
#endif
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
#if !defined(VBOX_WITH_IEM) || defined(VBOX_COMPARE_IEM_AND_EM)
DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
#endif
/*******************************************************************************
* Global Variables *
*******************************************************************************/
#ifdef VBOX_COMPARE_IEM_AND_EM
static bool g_fIgnoreRaxRdx = false;
#if defined(VBOX_COMPARE_IEM_FIRST) || defined(VBOX_COMPARE_IEM_LAST)
extern size_t g_cbIemWrote;
#else
#endif
#endif
/**
* Get the current execution manager status.
*
* @returns Current status.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Sets the current execution manager status. (use only when you know what you're doing!)
*
* @param pVCpu Pointer to the VMCPU.
*/
{
/* Only allowed combination: */
}
/**
* Sets the PC for which interrupts should be inhibited.
*
* @param pVCpu Pointer to the VMCPU.
* @param PC The PC.
*/
{
}
/**
* Gets the PC for which interrupts should be inhibited.
*
* There are a few instructions which inhibits or delays interrupts
* for the instruction following them. These instructions are:
* - STI
* - POP SS
*
* @returns The PC for which interrupts should be inhibited.
* @param pVCpu Pointer to the VMCPU.
*
*/
{
}
/**
* Prepare an MWAIT - essentials of the MONITOR instruction.
*
* @returns VINF_SUCCESS
* @param pVCpu The current CPU.
* @param rax The content of RAX.
* @param rcx The content of RCX.
* @param rdx The content of RDX.
* @param GCPhys The physical address corresponding to rax.
*/
VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
{
/** @todo Make use of GCPhys. */
/** @todo Complete MONITOR implementation. */
return VINF_SUCCESS;
}
/**
* Performs an MWAIT.
*
* @returns VINF_SUCCESS
* @param pVCpu The current CPU.
* @param rax The content of RAX.
* @param rcx The content of RCX.
*/
{
if (rcx)
else
/** @todo not completely correct?? */
return VINF_EM_HALT;
}
/**
* Determine if we should continue after encountering a mwait instruction.
*
* Clears MWAIT flags if returning @c true.
*
* @returns true if we should continue, false if we should halt.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Current CPU context.
*/
{
== (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0)) )
{
{
return true;
}
}
return false;
}
/**
* Determine if we should continue after encountering a hlt instruction.
*
* @returns true if we should continue, false if we should halt.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Current CPU context.
*/
{
return false;
}
/**
* Locks REM execution to a single VCPU.
*
* @param pVM Pointer to the VM.
*/
{
#ifdef VBOX_WITH_REM
return; /* early init */
#endif
}
/**
* Unlocks REM execution
*
* @param pVM Pointer to the VM.
*/
{
#ifdef VBOX_WITH_REM
return; /* early init */
#endif
}
/**
* Check if this VCPU currently owns the REM lock.
*
* @param pVM Pointer to the VM.
*/
{
#ifdef VBOX_WITH_REM
return true; /* early init */
#else
return true;
#endif
}
/**
* Try to acquire the REM lock.
*
* @returns VBox status code
* @param pVM Pointer to the VM.
*/
{
#ifdef VBOX_WITH_REM
return VINF_SUCCESS; /* early init */
#else
return VINF_SUCCESS;
#endif
}
/**
* @callback_method_impl{FNDISREADBYTES}
*/
static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
{
#endif
int rc;
/*
* Figure how much we can or must read.
*/
/*
* We might be called upon to interpret an instruction in a patch.
*/
{
# ifdef IN_RC
# else
# endif
rc = VINF_SUCCESS;
}
else
#endif
{
# ifdef IN_RC
/*
* Try access it thru the shadow page tables first. Fall back on the
* slower PGM method if it fails because the TLB or page table was
* modified recently.
*/
{
}
if (rc == VERR_ACCESS_DENIED)
#endif
{
if (RT_FAILURE(rc))
{
{
}
if (RT_FAILURE(rc))
{
#ifndef IN_RC
/*
* If we fail to find the page via the guest's page tables
* we invalidate the page in the host TLB (pertaining to
* the guest in the NestedPaging case). See @bugref{6043}.
*/
{
}
#endif
}
}
}
}
return rc;
}
DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
{
}
/**
* Disassembles the current instruction.
*
* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
* details.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pDis Where to return the parsed instruction info.
* @param pcbInstr Where to return the instruction size. (optional)
*/
VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
{
#if 0
#else
/** @todo Get the CPU mode as well while we're at it! */
int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
#endif
if (RT_FAILURE(rc))
{
Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
return rc;
}
}
/**
* Disassembles one instruction.
*
*
* @returns VBox status code.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param GCPtrInstr The flat address of the instruction.
* @param pCtxCore The context core (used to determine the cpu mode).
* @param pDis Where to return the parsed instruction info.
* @param pcbInstr Where to return the instruction size. (optional)
*/
VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
{
/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
if (RT_SUCCESS(rc))
return VINF_SUCCESS;
AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
return rc;
}
#if defined(VBOX_COMPARE_IEM_FIRST) || defined(VBOX_COMPARE_IEM_LAST)
{
/* Quick compare. */
&& g_cbEmWrote == g_cbIemWrote
)
return;
/* Report exact differences. */
{
if (g_cbIemWrote != g_cbEmWrote)
{
}
do \
{ \
{ \
{ \
case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
} \
cDiffs++; \
} \
} while (0)
do \
{ \
{ \
RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
cDiffs++; \
} \
} while (0)
do \
{ \
} while (0)
unsigned cDiffs = 0;
{
RTLogPrintf(" the FPU state differs\n");
cDiffs++;
}
{
}
if (!g_fIgnoreRaxRdx)
if (!g_fIgnoreRaxRdx)
CHECK_FIELD(dr[0]);
}
}
#endif /* VBOX_COMPARE_IEM_AND_EM */
/**
* Interprets the current instruction.
*
* @returns VBox status code.
* @retval VINF_* Scheduling instructions.
* @retval VERR_EM_INTERPRETER Something we can't cope with.
* @retval VERR_* Fatal errors.
*
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* Updates the EIP if an instruction was executed successfully.
* @param pvFault The fault address (CR2).
* @param pcbSize Size of the write (if applicable).
*
* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
* to worry about e.g. invalid modrm combinations (!)
*/
VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
{
#ifdef VBOX_WITH_IEM
# ifdef VBOX_COMPARE_IEM_AND_EM
g_IncomingCtx = *pCtx;
g_cbEmWrote = g_cbIemWrote = 0;
# ifdef VBOX_COMPARE_IEM_FIRST
/* IEM */
|| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) | (g_fIncomingFFs & g_fInterestingFFs);
*pCtx = g_IncomingCtx;
# endif
/* EM */
if (RT_SUCCESS(rcEm))
{
if (RT_SUCCESS(rcEm))
{
rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
if (RT_SUCCESS(rcEm))
}
}
else
# ifdef VBOX_SAME_AS_EM
if (rcEm == VERR_EM_INTERPRETER)
{
return rcEm;
}
# endif
# ifdef VBOX_COMPARE_IEM_LAST
/* IEM */
pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) | (g_fIncomingFFs & g_fInterestingFFs);
*pCtx = g_IncomingCtx;
|| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
# endif
# if defined(VBOX_COMPARE_IEM_LAST) || defined(VBOX_COMPARE_IEM_FIRST)
# endif
# else
|| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
# endif
if (rc != VINF_SUCCESS)
return rc;
#else
if (RT_SUCCESS(rc))
{
if (RT_SUCCESS(rc))
{
rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
if (RT_SUCCESS(rc))
return rc;
}
}
return VERR_EM_INTERPRETER;
#endif
}
/**
* Interprets the current instruction.
*
* @returns VBox status code.
* @retval VINF_* Scheduling instructions.
* @retval VERR_EM_INTERPRETER Something we can't cope with.
* @retval VERR_* Fatal errors.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* Updates the EIP if an instruction was executed successfully.
* @param pvFault The fault address (CR2).
* @param pcbWritten Size of the write (if applicable).
*
* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
* to worry about e.g. invalid modrm combinations (!)
*/
VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
{
#ifdef VBOX_WITH_IEM
# ifdef VBOX_COMPARE_IEM_AND_EM
g_IncomingCtx = *pCtx;
g_cbEmWrote = g_cbIemWrote = 0;
# ifdef VBOX_COMPARE_IEM_FIRST
/* IEM */
|| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) | (g_fIncomingFFs & g_fInterestingFFs);
*pCtx = g_IncomingCtx;
# endif
/* EM */
if (RT_SUCCESS(rcEm))
{
if (RT_SUCCESS(rcEm))
{
rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
if (RT_SUCCESS(rcEm))
}
else
}
else
# ifdef VBOX_SAME_AS_EM
if (rcEm == VERR_EM_INTERPRETER)
{
return rcEm;
}
# endif
# ifdef VBOX_COMPARE_IEM_LAST
/* IEM */
pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) | (g_fIncomingFFs & g_fInterestingFFs);
*pCtx = g_IncomingCtx;
|| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
# endif
# if defined(VBOX_COMPARE_IEM_LAST) || defined(VBOX_COMPARE_IEM_FIRST)
# endif
# else
|| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
# endif
if (rc != VINF_SUCCESS)
return rc;
#else
if (RT_SUCCESS(rc))
{
if (RT_SUCCESS(rc))
{
rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
if (RT_SUCCESS(rc))
return rc;
}
}
return VERR_EM_INTERPRETER;
#endif
}
/**
* Interprets the current instruction using the supplied DISCPUSTATE structure.
*
*
* @returns VBox strict status code.
* @retval VINF_* Scheduling instructions. When these are returned, it
* starts to get a bit tricky to know whether code was
* executed or not... We'll address this when it becomes a problem.
* @retval VERR_EM_INTERPRETER Something we can't cope with.
* @retval VERR_* Fatal errors.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pDis The disassembler cpu state for the instruction to be
* interpreted.
* @param pvFault The fault address (CR2).
* @param pcbSize Size of the write (if applicable).
* @param enmCodeType Code type (user/supervisor)
*
* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
* to worry about e.g. invalid modrm combinations (!)
*
* @todo At this time we do NOT check if the instruction overwrites vital information.
* Make sure this can't happen!! (will add some assertions/checks later)
*/
VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
{
#ifdef VBOX_WITH_IEM
# ifdef VBOX_COMPARE_IEM_AND_EM
g_IncomingCtx = *pCtx;
g_cbEmWrote = g_cbIemWrote = 0;
# ifdef VBOX_COMPARE_IEM_FIRST
VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
|| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) | (g_fIncomingFFs & g_fInterestingFFs);
*pCtx = g_IncomingCtx;
# endif
/* EM */
VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
if (RT_SUCCESS(rcEm))
# ifdef VBOX_SAME_AS_EM
if (rcEm == VERR_EM_INTERPRETER)
{
return rcEm;
}
# endif
# ifdef VBOX_COMPARE_IEM_LAST
/* IEM */
pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) | (g_fIncomingFFs & g_fInterestingFFs);
*pCtx = g_IncomingCtx;
VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
|| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
# endif
# if defined(VBOX_COMPARE_IEM_LAST) || defined(VBOX_COMPARE_IEM_FIRST)
# endif
# else
VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
|| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
# endif
if (rc != VINF_SUCCESS)
return rc;
#else
VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
if (RT_SUCCESS(rc))
return rc;
#endif
}
#ifdef IN_RC
DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
{
return rc;
}
/**
* Interpret IRET (currently only to V86 code) - PATM only.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
*
*/
{
int rc;
/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
* this function. Fear that it may guru on us, thus not converted to
* IEM. */
/* Mask away all reserved bits */
uMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_RF | X86_EFL_VM | X86_EFL_AC | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_ID;
return VINF_SUCCESS;
}
/**
* IRET Emulation.
*/
static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
#ifdef VBOX_WITH_RAW_RING1
if (EMIsRawRing1Enabled(pVM))
{
int rc;
/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
/* @todo: we don't verify all the edge cases that generate #GP faults */
/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
* this function. Fear that it may guru on us, thus not converted to
* IEM. */
/* Deal with V86 above. */
if (eflags & X86_EFL_VM)
{
}
/* Adjust CS & SS as required. */
/* Mask away all reserved bits */
uMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_RF | X86_EFL_VM | X86_EFL_AC | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_ID;
return VINF_SUCCESS;
}
#else
#endif
return VERR_EM_INTERPRETER;
}
#endif /* IN_RC */
/*
*
*
*/
/**
* Interpret CPUID given the parameters in the CPU context.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
*
*/
{
/* cpuid clears the high dwords of the affected 64 bits registers. */
/* Note: operates the same in 64 and non-64 bits mode. */
CPUMGetGuestCpuId(pVCpu, iLeaf, iSubLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
return VINF_SUCCESS;
}
/**
* Interpret RDTSC.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
*
*/
{
if (uCR4 & X86_CR4_TSD)
return VERR_EM_INTERPRETER; /* genuine #GP */
/* Same behaviour in 32 & 64 bits mode */
#ifdef VBOX_COMPARE_IEM_AND_EM
g_fIgnoreRaxRdx = true;
#endif
return VINF_SUCCESS;
}
/**
* Interpret RDTSCP.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx The CPU context.
*
*/
{
{
AssertFailed();
return VERR_EM_INTERPRETER; /* genuine #UD */
}
if (uCR4 & X86_CR4_TSD)
return VERR_EM_INTERPRETER; /* genuine #GP */
/* Same behaviour in 32 & 64 bits mode */
#ifdef VBOX_COMPARE_IEM_AND_EM
g_fIgnoreRaxRdx = true;
#endif
/* Low dword of the TSC_AUX msr only. */
VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS);
return VINF_SUCCESS;
}
/**
* Interpret RDPMC.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
*
*/
{
/* If X86_CR4_PCE is not set, then CPL must be zero. */
if ( !(uCR4 & X86_CR4_PCE)
&& CPUMGetGuestCPL(pVCpu) != 0)
{
return VERR_EM_INTERPRETER; /* genuine #GP */
}
/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
/** @todo We should trigger a #GP here if the CPU doesn't support the index in ecx
* but see @bugref{3472}! */
return VINF_SUCCESS;
}
/**
* MWAIT Emulation.
*/
{
/* Get the current privilege level. */
if (cpl != 0)
return VERR_EM_INTERPRETER; /* supervisor only */
if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
return VERR_EM_INTERPRETER; /* not supported */
/*
* CPUID.05H.ECX[0] defines support for power management extensions (eax)
* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
*/
{
return VERR_EM_INTERPRETER; /* illegal value. */
}
{
Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
return VERR_EM_INTERPRETER; /* illegal value. */
}
}
/**
* MONITOR Emulation.
*/
{
{
return VERR_EM_INTERPRETER; /* illegal value. */
}
/* Get the current privilege level. */
if (cpl != 0)
return VERR_EM_INTERPRETER; /* supervisor only */
if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
return VERR_EM_INTERPRETER; /* not supported */
return VINF_SUCCESS;
}
/* VT-x only: */
/**
* Interpret INVLPG.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* @param pAddrGC Operand address.
*
*/
VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
{
/** @todo is addr always a flat linear address or ds based
* (in absence of segment override prefixes)????
*/
#ifdef IN_RC
#endif
if ( rc == VINF_SUCCESS
return VINF_SUCCESS;
return rc;
}
/**
* Update CRx.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
* @param val New CRx value
*
*/
static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
{
/** @todo Clean up this mess. */
switch (DestRegCrx)
{
case DISCREG_CR0:
#ifdef IN_RC
/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
return VERR_EM_INTERPRETER;
#endif
rc = VINF_SUCCESS;
#if !defined(VBOX_COMPARE_IEM_AND_EM) || !defined(VBOX_COMPARE_IEM_LAST)
#else
#endif
{
/* global flush */
}
if (msrEFER & MSR_K6_EFER_LME)
{
if ( !(oldval & X86_CR0_PG)
&& (val & X86_CR0_PG))
{
/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
{
AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
}
/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
{
AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
}
}
else
if ( (oldval & X86_CR0_PG)
&& !(val & X86_CR0_PG))
{
msrEFER &= ~MSR_K6_EFER_LMA;
/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
}
}
rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
case DISCREG_CR2:
return VINF_SUCCESS;
case DISCREG_CR3:
/* Reloading the current CR3 means the guest just wants to flush the TLBs */
{
/* flush */
}
return rc;
case DISCREG_CR4:
/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
if ( (msrEFER & MSR_K6_EFER_LMA)
&& (oldval & X86_CR4_PAE)
&& !(val & X86_CR4_PAE))
{
return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
}
/* From IEM iemCImpl_load_CrX. */
/** @todo Check guest CPUID bits for determining corresponding valid bits. */
//if (xxx)
// fValid |= X86_CR4_VMXE;
//if (xxx)
// fValid |= X86_CR4_OSXSAVE;
{
Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", val, val & ~(uint64_t)fValid));
return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
}
rc = VINF_SUCCESS;
{
/* global flush */
}
/* Feeling extremely lazy. */
# ifdef IN_RC
if ( (oldval & (X86_CR4_OSFXSR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME))
!= (val & (X86_CR4_OSFXSR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME)))
{
}
# endif
# ifdef VBOX_WITH_RAW_MODE
# endif
rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
case DISCREG_CR8:
return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
default:
AssertFailed();
case DISCREG_CR1: /* illegal op */
break;
}
return VERR_EM_INTERPRETER;
}
/**
* Interpret CRx write.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
* @param SrcRegGen General purpose register index (USE_REG_E**))
*
*/
static int emInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
{
int rc;
if (CPUMIsGuestIn64BitCode(pVCpu))
else
{
}
if (RT_SUCCESS(rc))
return VERR_EM_INTERPRETER;
}
#ifdef LOG_ENABLED
{
switch (uMsr)
{
case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
case MSR_K6_EFER: return "MSR_K6_EFER";
case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
case MSR_K6_STAR: return "MSR_K6_STAR";
case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
case MSR_IA32_TSC: return "MSR_IA32_TSC";
case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
}
return "Unknown MSR";
}
#endif /* LOG_ENABLED */
/**
* Interpret RDMSR
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
*/
{
/* Get the current privilege level. */
if (CPUMGetGuestCPL(pVCpu) != 0)
{
Log4(("EM: Refuse RDMSR: CPL != 0\n"));
return VERR_EM_INTERPRETER; /* supervisor only */
}
{
Assert(rcStrict == VERR_CPUM_RAISE_GP_0 || rcStrict == VERR_EM_INTERPRETER || rcStrict == VINF_CPUM_R3_MSR_READ);
return VERR_EM_INTERPRETER;
}
LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
return VINF_SUCCESS;
}
/**
* Interpret WRMSR
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
*/
{
/* Check the current privilege level, this instruction is supervisor only. */
if (CPUMGetGuestCPL(pVCpu) != 0)
{
Log4(("EM: Refuse WRMSR: CPL != 0\n"));
return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
}
VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
if (rcStrict != VINF_SUCCESS)
{
Assert(rcStrict == VERR_CPUM_RAISE_GP_0 || rcStrict == VERR_EM_INTERPRETER || rcStrict == VINF_CPUM_R3_MSR_WRITE);
return VERR_EM_INTERPRETER;
}
return VINF_SUCCESS;
}
/**
* Interpret CRx read.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* @param DestRegGen General purpose register index (USE_REG_E**))
* @param SrcRegCRx CRx register index (DISUSE_REG_CR*)
*
*/
static int emInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
{
if (CPUMIsGuestIn64BitCode(pVCpu))
else
if (RT_SUCCESS(rc))
{
return VINF_SUCCESS;
}
return VERR_EM_INTERPRETER;
}
/**
* Interpret DRx write.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* @param DestRegDRx DRx register index (USE_REG_DR*)
* @param SrcRegGen General purpose register index (USE_REG_E**))
*
*/
VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
{
int rc;
if (CPUMIsGuestIn64BitCode(pVCpu))
else
{
}
if (RT_SUCCESS(rc))
{
if (DestRegDrx == 6)
{
uNewDrX &= ~X86_DR6_RAZ_MASK;
}
else if (DestRegDrx == 7)
{
uNewDrX &= ~X86_DR7_RAZ_MASK;
}
if (RT_SUCCESS(rc))
return rc;
}
return VERR_EM_INTERPRETER;
}
/**
* Interpret DRx read.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame The register frame.
* @param DestRegGen General purpose register index (USE_REG_E**))
* @param SrcRegDRx DRx register index (USE_REG_DR*)
*
*/
VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
{
if (CPUMIsGuestIn64BitCode(pVCpu))
else
if (RT_SUCCESS(rc))
return VINF_SUCCESS;
return VERR_EM_INTERPRETER;
}
#if !defined(VBOX_WITH_IEM) || defined(VBOX_COMPARE_IEM_AND_EM)
/*
*
* The old interpreter.
* The old interpreter.
* The old interpreter.
* The old interpreter.
* The old interpreter.
*
*/
DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
{
#ifdef IN_RC
return rc;
/*
* The page pool cache may end up here in some cases because it
* flushed one of the shadow mappings used by the trapping
* instruction and it either flushed the TLB or the CPU reused it.
*/
#else
#endif
}
DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
{
/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
pages or write monitored pages. */
#if !defined(VBOX_COMPARE_IEM_AND_EM) || !defined(VBOX_COMPARE_IEM_LAST)
int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /*fMayTrap*/ false);
#else
#endif
#ifdef VBOX_COMPARE_IEM_AND_EM
g_cbEmWrote = cb;
#endif
return rc;
}
/** Convert sel:addr to a flat GC address. */
DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
{
}
#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
/**
* Get the mnemonic for the disassembled instruction.
*
* of limited space.
*/
{
{
case OP_XCHG: return "Xchg";
case OP_DEC: return "Dec";
case OP_INC: return "Inc";
case OP_POP: return "Pop";
case OP_OR: return "Or";
case OP_AND: return "And";
case OP_MOV: return "Mov";
case OP_INVLPG: return "InvlPg";
case OP_CPUID: return "CpuId";
case OP_MOV_CR: return "MovCRx";
case OP_MOV_DR: return "MovDRx";
case OP_LLDT: return "LLdt";
case OP_LGDT: return "LGdt";
case OP_LIDT: return "LIdt";
case OP_CLTS: return "Clts";
case OP_MONITOR: return "Monitor";
case OP_MWAIT: return "MWait";
case OP_RDMSR: return "Rdmsr";
case OP_WRMSR: return "Wrmsr";
case OP_ADD: return "Add";
case OP_ADC: return "Adc";
case OP_SUB: return "Sub";
case OP_SBB: return "Sbb";
case OP_RDTSC: return "Rdtsc";
case OP_STI: return "Sti";
case OP_CLI: return "Cli";
case OP_XADD: return "XAdd";
case OP_HLT: return "Hlt";
case OP_IRET: return "Iret";
case OP_MOVNTPS: return "MovNTPS";
case OP_STOSWD: return "StosWD";
case OP_WBINVD: return "WbInvd";
case OP_XOR: return "Xor";
case OP_BTR: return "Btr";
case OP_BTS: return "Bts";
case OP_BTC: return "Btc";
case OP_LMSW: return "Lmsw";
case OP_SMSW: return "Smsw";
default:
return "???";
}
}
#endif /* VBOX_STRICT || LOG_ENABLED */
/**
* XCHG instruction emulation.
*/
static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
/* Source to make DISQueryParamVal read the register value - ugly hack */
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
#ifdef IN_RC
if (TRPMHasTrap(pVCpu))
{
{
#endif
{
case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
break;
case DISQPV_TYPE_ADDRESS:
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
{
case DISQPV_TYPE_ADDRESS:
if (RT_FAILURE(rc))
{
}
break;
case DISQPV_TYPE_IMMEDIATE:
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
/* Write value of parameter 2 to parameter 1 (reg or memory address) */
if (pParam1 == 0)
{
{
case 1: //special case for AH etc
default: AssertFailedReturn(VERR_EM_INTERPRETER);
}
if (RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
}
else
{
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
}
/* Write value of parameter 1 to parameter 2 (reg or memory address) */
if (pParam2 == 0)
{
{
case 1: //special case for AH etc
default: AssertFailedReturn(VERR_EM_INTERPRETER);
}
if (RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
}
else
{
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
}
return VINF_SUCCESS;
#ifdef IN_RC
}
}
return VERR_EM_INTERPRETER;
#endif
}
/**
* INC and DEC emulation.
*/
static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
#ifdef IN_RC
if (TRPMHasTrap(pVCpu))
{
{
#endif
{
#ifdef IN_RC
/* Safety check (in theory it could cross a page boundary and fault there though) */
#endif
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
}
else
{
AssertFailed();
return VERR_EM_INTERPRETER;
}
/* Write result back */
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
/* All done! */
return VINF_SUCCESS;
#ifdef IN_RC
}
}
return VERR_EM_INTERPRETER;
#endif
}
/**
* POP Emulation.
*/
static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
#ifdef IN_RC
if (TRPMHasTrap(pVCpu))
{
{
#endif
/* Read stack value first */
return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
/* Convert address; don't bother checking limits etc, as we only read here */
if (pStackVal == 0)
return VERR_EM_INTERPRETER;
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
{
/* pop [esp+xx] uses esp after the actual pop! */
)
EM_ASSERT_FAULT_RETURN(pParam1 == pvFault || (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
/* Update ESP as the last step */
}
else
{
#ifndef DEBUG_bird // annoying assertion.
AssertFailed();
#endif
return VERR_EM_INTERPRETER;
}
/* All done! */
return VINF_SUCCESS;
#ifdef IN_RC
}
}
return VERR_EM_INTERPRETER;
#endif
}
/**
*/
static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
#ifdef IN_RC
if (TRPMHasTrap(pVCpu))
{
{
#endif
{
{
AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
return VERR_EM_INTERPRETER;
}
/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
}
/* The destination is always a virtual address */
{
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
}
else
{
AssertFailed();
return VERR_EM_INTERPRETER;
}
/* Register or immediate data */
{
case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
/* Data read, emulate instruction. */
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
/* And write it back */
if (RT_SUCCESS(rc))
{
/* All done! */
return VINF_SUCCESS;
}
#ifdef IN_RC
}
}
#endif
return VERR_EM_INTERPRETER;
}
#ifndef VBOX_COMPARE_IEM_AND_EM
/**
*/
static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
{
void *pvParam1;
#endif
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
}
#ifdef IN_RC
/* Safety check (in theory it could cross a page boundary and fault there though) */
#endif
/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
/* The destination is always a virtual address */
/* Try emulate it with a one-shot #PF handler in place. (RC) */
if (RT_FAILURE(rc))
{
Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
return VERR_EM_INTERPRETER;
}
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
return VINF_SUCCESS;
}
#endif /* !VBOX_COMPARE_IEM_AND_EM */
/**
* ADD, ADC & SUB Emulation.
*/
static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
#ifdef IN_RC
if (TRPMHasTrap(pVCpu))
{
{
#endif
{
{
AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
return VERR_EM_INTERPRETER;
}
/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
}
/* The destination is always a virtual address */
{
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
}
else
{
#ifndef DEBUG_bird
AssertFailed();
#endif
return VERR_EM_INTERPRETER;
}
/* Register or immediate data */
{
case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
/* Data read, emulate instruction. */
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
/* And write it back */
if (RT_SUCCESS(rc))
{
/* All done! */
return VINF_SUCCESS;
}
#ifdef IN_RC
}
}
#endif
return VERR_EM_INTERPRETER;
}
/**
* ADC Emulation.
*/
static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
else
}
/**
* BTR/C/S Emulation.
*/
static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
#ifdef IN_RC
if (TRPMHasTrap(pVCpu))
{
{
#endif
/* The destination is always a virtual address */
return VERR_EM_INTERPRETER;
/* Register or immediate data */
{
case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
/* Data read, emulate bit test instruction. */
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
/* And write it back */
if (RT_SUCCESS(rc))
{
/* All done! */
*pcbSize = 1;
return VINF_SUCCESS;
}
#ifdef IN_RC
}
}
#endif
return VERR_EM_INTERPRETER;
}
#ifndef VBOX_COMPARE_IEM_AND_EM
/**
* LOCK BTR/C/S Emulation.
*/
static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
{
void *pvParam1;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
/* The destination is always a virtual address */
return VERR_EM_INTERPRETER;
/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
ValPar2 &= 7;
#ifdef IN_RC
EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
#endif
Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
/* Try emulate it with a one-shot #PF handler in place. (RC) */
if (RT_FAILURE(rc))
{
Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
return VERR_EM_INTERPRETER;
}
Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
*pcbSize = 1;
return VINF_SUCCESS;
}
#endif /* !VBOX_COMPARE_IEM_AND_EM */
/**
* MOV emulation.
*/
static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
/* If destination is a segment register, punt. We can't handle it here.
* NB: Source can be a register and still trigger a #PF!
*/
return VERR_EM_INTERPRETER;
{
{
case DISQPV_TYPE_IMMEDIATE:
return VERR_EM_INTERPRETER;
/* fallthru */
case DISQPV_TYPE_ADDRESS:
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
{
case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
break;
default:
return VERR_EM_INTERPRETER;
}
#ifdef LOG_ENABLED
LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
else
LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
#endif
if (RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
}
#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
{
AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
{
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
}
#endif
else
{ /* read fault */
/* Source */
{
case DISQPV_TYPE_IMMEDIATE:
return VERR_EM_INTERPRETER;
/* fallthru */
case DISQPV_TYPE_ADDRESS:
break;
default:
return VERR_EM_INTERPRETER;
}
if (RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
/* Destination */
{
case DISQPV_TYPE_REGISTER:
{
default:
return VERR_EM_INTERPRETER;
}
if (RT_FAILURE(rc))
return rc;
break;
default:
return VERR_EM_INTERPRETER;
}
#ifdef LOG_ENABLED
else
LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
#endif
}
return VINF_SUCCESS;
}
#ifndef IN_RC
/**
* [REP] STOSWD emulation
*/
static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
int rc;
int offIncrement;
/* Don't support any but these three prefix bytes. */
return VERR_EM_INTERPRETER;
{
case DISCPUMODE_16BIT:
break;
case DISCPUMODE_32BIT:
break;
case DISCPUMODE_64BIT:
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
{
case DISCPUMODE_16BIT:
cbSize = 2;
break;
case DISCPUMODE_32BIT:
cbSize = 4;
break;
case DISCPUMODE_64BIT:
cbSize = 8;
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
{
LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
if (RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
/* Update (e/r)di. */
{
case DISCPUMODE_16BIT:
break;
case DISCPUMODE_32BIT:
break;
case DISCPUMODE_64BIT:
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
}
else
{
if (!cTransfers)
return VINF_SUCCESS;
/*
* Do *not* try emulate cross page stuff here because we don't know what might
* be waiting for us on the subsequent pages. The caller has only asked us to
* ignore access handlers fro the current page.
* This also fends off big stores which would quickly kill PGMR0DynMap.
*/
|| cTransfers > PAGE_SIZE
{
Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
return VERR_EM_INTERPRETER;
}
LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
/* Access verification first; we currently can't recover properly from traps inside this instruction */
cTransfers * cbSize,
if (rc != VINF_SUCCESS)
{
return VERR_EM_INTERPRETER;
}
/* REP case */
while (cTransfers)
{
if (RT_FAILURE(rc))
{
break;
}
GCOffset += offIncrement;
GCDest += offIncrement;
cTransfers--;
}
/* Update the registers. */
{
case DISCPUMODE_16BIT:
break;
case DISCPUMODE_32BIT:
break;
case DISCPUMODE_64BIT:
break;
default:
AssertFailed();
return VERR_EM_INTERPRETER;
}
}
return rc;
}
#endif /* !IN_RC */
/**
* [LOCK] CMPXCHG emulation.
*/
static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
#endif
/* Source to make DISQueryParamVal read the register value - ugly hack */
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case DISQPV_TYPE_IMMEDIATE: /* register actually */
break;
default:
return VERR_EM_INTERPRETER;
}
void *pvParam1;
{
case DISQPV_TYPE_ADDRESS:
break;
default:
return VERR_EM_INTERPRETER;
}
#ifndef VBOX_COMPARE_IEM_AND_EM
else
#else /* VBOX_COMPARE_IEM_AND_EM */
{
default:
}
int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
#endif /* VBOX_COMPARE_IEM_AND_EM */
LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
return VINF_SUCCESS;
}
/**
* [LOCK] CMPXCHG8B emulation.
*/
static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
/* Source to make DISQueryParamVal read the register value - ugly hack */
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
void *pvParam1;
{
case DISQPV_TYPE_ADDRESS:
break;
default:
return VERR_EM_INTERPRETER;
}
#ifndef VBOX_COMPARE_IEM_AND_EM
eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
else
eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
#else /* VBOX_COMPARE_IEM_AND_EM */
eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
#endif /* VBOX_COMPARE_IEM_AND_EM */
LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
/* Update guest's eflags and finish; note that *only* ZF is affected. */
| (eflags & (X86_EFL_ZF));
*pcbSize = 8;
return VINF_SUCCESS;
}
#ifdef IN_RC /** @todo test+enable for HM as well. */
/**
* [LOCK] XADD emulation.
*/
static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
void *pvParamReg2;
/* Source to make DISQueryParamVal read the register value - ugly hack */
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
#ifdef IN_RC
if (TRPMHasTrap(pVCpu))
{
{
#endif
void *pvParam1;
{
case DISQPV_TYPE_ADDRESS:
GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
#ifdef IN_RC
#endif
break;
default:
return VERR_EM_INTERPRETER;
}
#ifndef VBOX_COMPARE_IEM_AND_EM
else
#else /* VBOX_COMPARE_IEM_AND_EM */
switch (cbParamReg2)
{
default:
}
int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
#endif /* VBOX_COMPARE_IEM_AND_EM */
LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, *(uint64_t *)pvParamReg2, !!(eflags & X86_EFL_ZF) ));
/* Update guest's eflags and finish. */
pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
*pcbSize = cbParamReg2;
return VINF_SUCCESS;
#ifdef IN_RC
}
}
return VERR_EM_INTERPRETER;
#endif
}
#endif /* IN_RC */
/**
* WBINVD Emulation.
*/
static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
/* Nothing to do. */
return VINF_SUCCESS;
}
/**
* INVLPG Emulation.
*/
static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case DISQPV_TYPE_IMMEDIATE:
case DISQPV_TYPE_ADDRESS:
return VERR_EM_INTERPRETER;
break;
default:
return VERR_EM_INTERPRETER;
}
/** @todo is addr always a flat linear address or ds based
* (in absence of segment override prefixes)????
*/
#ifdef IN_RC
#endif
if ( rc == VINF_SUCCESS
return VINF_SUCCESS;
return rc;
}
/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
/**
* CPUID Emulation.
*/
static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
return rc;
}
/**
* CLTS Emulation.
*/
static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if (!(cr0 & X86_CR0_TS))
return VINF_SUCCESS;
}
/**
* LMSW Emulation.
*/
static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case DISQPV_TYPE_IMMEDIATE:
case DISQPV_TYPE_ADDRESS:
return VERR_EM_INTERPRETER;
break;
default:
return VERR_EM_INTERPRETER;
}
/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
}
#ifdef EM_EMULATE_SMSW
/**
* SMSW Emulation.
*/
static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case DISQPV_TYPE_IMMEDIATE:
return VERR_EM_INTERPRETER;
break;
case DISQPV_TYPE_ADDRESS:
{
/* Actually forced to 16 bits regardless of the operand size. */
return VERR_EM_INTERPRETER;
if (RT_FAILURE(rc))
{
return VERR_EM_INTERPRETER;
}
break;
}
default:
return VERR_EM_INTERPRETER;
}
return rc;
}
#endif
/**
* MOV CRx
*/
static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if ((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
return emInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
return emInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
}
/**
* MOV DRx
*/
static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
{
rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
}
else
if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
{
rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
}
else
AssertMsgFailed(("Unexpected debug register move\n"));
return rc;
}
/**
* LLDT Emulation.
*/
static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case DISQPV_TYPE_ADDRESS:
return VERR_EM_INTERPRETER; //feeling lazy right now
case DISQPV_TYPE_IMMEDIATE:
return VERR_EM_INTERPRETER;
break;
default:
return VERR_EM_INTERPRETER;
}
#ifdef IN_RING0
/* Only for the VT-x real-mode emulation case. */
return VINF_SUCCESS;
#else
if (sel == 0)
{
if (CPUMGetHyperLDTR(pVCpu) == 0)
{
// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
return VINF_SUCCESS;
}
}
//still feeling lazy
return VERR_EM_INTERPRETER;
#endif
}
#ifdef IN_RING0
/**
*/
static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
/* Only for the VT-x real-mode emulation case. */
if(RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case DISQPV_TYPE_ADDRESS:
break;
default:
return VERR_EM_INTERPRETER;
}
else
return VINF_SUCCESS;
}
#endif
#ifdef IN_RC
/**
* STI Emulation.
*
* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
*/
static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
if(!pGCState)
{
return VERR_EM_INTERPRETER;
}
return VINF_SUCCESS;
}
#endif /* IN_RC */
/**
* HLT Emulation.
*/
static VBOXSTRICTRC
emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
return VINF_EM_HALT;
}
/**
* RDTSC Emulation.
*/
static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
}
/**
* RDPMC Emulation
*/
static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
}
static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
}
static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
}
/**
* RDMSR Emulation.
*/
static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
different, so we play safe by completely disassembling the instruction. */
}
/**
* WRMSR Emulation.
*/
static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
{
}
/**
* Internal worker.
* @copydoc emInterpretInstructionCPUOuter
*/
DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
{
*pcbSize = 0;
if (enmCodeType == EMCODETYPE_SUPERVISOR)
{
/*
* Only supervisor guest code!!
* And no complicated prefixes.
*/
/* Get the current privilege level. */
#ifdef VBOX_WITH_RAW_RING1
if ( !EMIsRawRing1Enabled(pVM)
|| cpl > 1
)
#endif
{
if ( cpl != 0
{
Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
return VERR_EM_INTERPRETER;
}
}
}
else
Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
#ifdef IN_RC
)
)
#else
)
)
)
#endif
{
//Log(("EMInterpretInstruction: wrong prefix!!\n"));
return VERR_EM_INTERPRETER;
}
#if HC_ARCH_BITS == 32
/*
* Unable to emulate most >4 bytes accesses in 32 bits mode.
* Whitelisted instructions are safe.
*/
{
&& uOpCode != OP_CMPXCHG8B
/** @todo OP_BTS or is that a different kind of failure? */
# endif
)
{
# ifdef VBOX_WITH_STATISTICS
{
default:
break;
}
# endif /* VBOX_WITH_STATISTICS */
Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
return VERR_EM_INTERPRETER;
}
}
#endif
#if (defined(VBOX_STRICT) || defined(LOG_ENABLED))
#endif
{
/*
* Macros for generating the right case statements.
*/
# ifndef VBOX_COMPARE_IEM_AND_EM
case opcode:\
else \
if (RT_SUCCESS(rc)) \
else \
return rc
# else /* VBOX_COMPARE_IEM_AND_EM */
case opcode:\
if (RT_SUCCESS(rc)) \
else \
return rc
# endif /* VBOX_COMPARE_IEM_AND_EM */
case opcode:\
if (RT_SUCCESS(rc)) \
else \
return rc
case opcode:\
if (RT_SUCCESS(rc)) \
else \
return rc
case opcode:\
if (RT_SUCCESS(rc)) \
else \
return rc
case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
/*
* The actual case statements.
*/
#ifndef IN_RC
#endif
#ifdef IN_RING0
#endif
#ifdef EM_EMULATE_SMSW
#endif
#ifdef IN_RC
#endif
#ifdef VBOX_WITH_STATISTICS
# ifndef IN_RC
# endif
#endif
default:
return VERR_EM_INTERPRETER;
} /* switch (opcode) */
/* not reached */
}
/**
* Interprets the current instruction using the supplied DISCPUSTATE structure.
*
* EIP is *NOT* updated!
*
* @returns VBox strict status code.
* @retval VINF_* Scheduling instructions. When these are returned, it
* starts to get a bit tricky to know whether code was
* executed or not... We'll address this when it becomes a problem.
* @retval VERR_EM_INTERPRETER Something we can't cope with.
* @retval VERR_* Fatal errors.
*
* @param pVCpu Pointer to the VMCPU.
* @param pDis The disassembler cpu state for the instruction to be
* interpreted.
* @param pRegFrame The register frame. EIP is *NOT* changed!
* @param pvFault The fault address (CR2).
* @param pcbSize Size of the write (if applicable).
* @param enmCodeType Code type (user/supervisor)
*
* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
* to worry about e.g. invalid modrm combinations (!)
*
* @todo At this time we do NOT check if the instruction overwrites vital information.
* Make sure this can't happen!! (will add some assertions/checks later)
*/
DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
{
VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
if (RT_SUCCESS(rc))
else
return rc;
}
#endif /* !VBOX_WITH_IEM */