| /openjdk7/hotspot/src/cpu/sparc/vm/ |
| H A D | assembler_sparc.hpp | 591 arith_op = 2, // fmt 3, arith & misc enumerator in enum:Assembler::ops
1238 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1239 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1240 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
1241 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1242 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1243 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1301 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
1302 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1303 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | r
[all...] |
| H A D | nativeInst_sparc.cpp | 113 if (is_op3(x, temp, Assembler::arith_op) &&
164 assert(inv_op(*contention_addr) == Assembler::arith_op ||
183 assert(inv_op(*contention_addr) == Assembler::arith_op ||
312 is_op3(i1, Assembler::add_op3, Assembler::arith_op) &&
429 is_op3(i2, Assembler::add_op3, Assembler::arith_op) &&
827 (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) ||
828 (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) &&
941 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
959 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
1006 assert(inv_op(*contention_addr) == Assembler::arith_op ||
[all...] |
| H A D | relocInfo_sparc.cpp | 68 case Assembler::arith_op:
110 guarantee(Assembler::inv_op(inst2)==Assembler::arith_op, "arith op");
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| H A D | nativeInst_sparc.hpp | 66 return (is_op(x, Assembler::arith_op) &&
84 return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
121 return is_op3(x, Assembler::membar_op3, Assembler::arith_op) &&
140 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); }
143 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | u_field(5, 18, 14) | Assembler::rd(O7); }
233 Assembler::arith_op, Assembler::ldst_op) && member in class:VALUE_OBJ_CLASS_SPEC::Assembler
298 assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" );
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| H A D | assembler_sparc.inline.hpp | 79 inline void Assembler::add(Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
80 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
81 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
108 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
109 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
111 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { cti(); emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
112 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { cti(); emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
247 inline void Assembler::rett( Register s1, Register s2 ) { cti(); emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
248 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { cti(); emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
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| H A D | c1_LIRAssembler_sparc.cpp | 1784 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { function in class:LIR_Assembler
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| /openjdk7/hotspot/src/share/vm/c1/ |
| H A D | c1_LIRAssembler.hpp | 207 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
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| H A D | c1_LIRAssembler.cpp | 735 arith_op(
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| /openjdk7/hotspot/src/cpu/x86/vm/ |
| H A D | c1_LIRAssembler_x86.cpp | 2046 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { function in class:LIR_Assembler
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