0N/A

1879N/A#ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP

1879N/A#define SHARE_VM_C1_C1_LIRASSEMBLER_HPP

1879N/A

1879N/A#include "c1/c1_CodeStubs.hpp"

1879N/A#include "ci/ciMethodData.hpp"

1879N/A#include "oops/methodDataOop.hpp"

1879N/A#include "utilities/top.hpp"

1879N/A

0N/Aclass Compilation;

0N/Aclass ScopeValue;

342N/Aclass BarrierSet;

0N/A

0N/Aclass LIR_Assembler: public CompilationResourceObj {

0N/A private:

0N/A C1_MacroAssembler* _masm;

0N/A CodeStubList* _slow_case_stubs;

342N/A BarrierSet* _bs;

0N/A

0N/A Compilation* _compilation;

0N/A FrameMap* _frame_map;

0N/A BlockBegin* _current_block;

0N/A

0N/A Instruction* _pending_non_safepoint;

0N/A int _pending_non_safepoint_offset;

0N/A

1378N/A Label _unwind_handler_entry;

1378N/A

0N/A#ifdef ASSERT

0N/A BlockList _branch_target_blocks;

0N/A void check_no_unbound_labels();

0N/A#endif

0N/A

0N/A FrameMap* frame_map() const { return _frame_map; }

0N/A

0N/A void set_current_block(BlockBegin* b) { _current_block = b; }

0N/A BlockBegin* current_block() const { return _current_block; }

0N/A

0N/A // non-safepoint debug info management

0N/A void flush_debug_info(int before_pc_offset) {

0N/A if (_pending_non_safepoint != NULL) {

0N/A if (_pending_non_safepoint_offset < before_pc_offset)

0N/A record_non_safepoint_debug_info();

0N/A _pending_non_safepoint = NULL;

0N/A }

0N/A }

0N/A void process_debug_info(LIR_Op* op);

0N/A void record_non_safepoint_debug_info();

0N/A

0N/A // unified bailout support

0N/A void bailout(const char* msg) const { compilation()->bailout(msg); }

0N/A bool bailed_out() const { return compilation()->bailed_out(); }

0N/A

0N/A // code emission patterns and accessors

0N/A void check_codespace();

0N/A bool needs_icache(ciMethod* method) const;

0N/A

0N/A // returns offset of icache check

0N/A int check_icache();

0N/A

0N/A void jobject2reg(jobject o, Register reg);

0N/A void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);

0N/A

0N/A void emit_stubs(CodeStubList* stub_list);

0N/A

0N/A // addresses

304N/A Address as_Address(LIR_Address* addr);

304N/A Address as_Address_lo(LIR_Address* addr);

304N/A Address as_Address_hi(LIR_Address* addr);

0N/A

0N/A // debug information

1484N/A void add_call_info(int pc_offset, CodeEmitInfo* cinfo);

0N/A void add_debug_info_for_branch(CodeEmitInfo* info);

0N/A void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);

0N/A void add_debug_info_for_div0_here(CodeEmitInfo* info);

0N/A void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);

0N/A void add_debug_info_for_null_check_here(CodeEmitInfo* info);

0N/A

0N/A void set_24bit_FPU();

0N/A void reset_FPU();

0N/A void fpop();

0N/A void fxch(int i);

0N/A void fld(int i);

0N/A void ffree(int i);

0N/A

0N/A void breakpoint();

0N/A void push(LIR_Opr opr);

0N/A void pop(LIR_Opr opr);

0N/A

0N/A // patching

0N/A void append_patching_stub(PatchingStub* stub);

0N/A void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);

0N/A

0N/A void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);

0N/A

0N/A public:

0N/A LIR_Assembler(Compilation* c);

0N/A ~LIR_Assembler();

0N/A C1_MacroAssembler* masm() const { return _masm; }

0N/A Compilation* compilation() const { return _compilation; }

0N/A ciMethod* method() const { return compilation()->method(); }

0N/A

0N/A CodeOffsets* offsets() const { return _compilation->offsets(); }

0N/A int code_offset() const;

0N/A address pc() const;

0N/A

0N/A int initial_frame_size_in_bytes();

0N/A

0N/A // test for constants which can be encoded directly in instructions

0N/A static bool is_small_constant(LIR_Opr opr);

0N/A

0N/A static LIR_Opr receiverOpr();

0N/A static LIR_Opr osrBufferPointer();

0N/A

0N/A // stubs

0N/A void emit_slow_case_stubs();

0N/A void emit_static_call_stub();

0N/A void emit_code_stub(CodeStub* op);

0N/A void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); }

0N/A

0N/A // code patterns

1204N/A int emit_exception_handler();

1378N/A int emit_unwind_handler();

0N/A void emit_exception_entries(ExceptionInfoList* info_list);

1204N/A int emit_deopt_handler();

0N/A

0N/A void emit_code(BlockList* hir);

0N/A void emit_block(BlockBegin* block);

0N/A void emit_lir_list(LIR_List* list);

0N/A

0N/A // any last minute peephole optimizations are performed here. In

0N/A // particular sparc uses this for delay slot filling.

0N/A void peephole(LIR_List* list);

0N/A

0N/A void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info);

0N/A

0N/A void return_op(LIR_Opr result);

0N/A

0N/A // returns offset of poll instruction

0N/A int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);

0N/A

0N/A void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);

0N/A void const2stack(LIR_Opr src, LIR_Opr dest);

1909N/A void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide);

0N/A void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);

0N/A void reg2reg (LIR_Opr src, LIR_Opr dest);

1909N/A void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type,

1909N/A LIR_PatchCode patch_code, CodeEmitInfo* info,

1909N/A bool pop_fpu_stack, bool wide, bool unaligned);

0N/A void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type);

0N/A void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);

0N/A void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type,

1909N/A LIR_PatchCode patch_code,

1909N/A CodeEmitInfo* info, bool wide, bool unaligned);

0N/A

0N/A void prefetchr (LIR_Opr src);

0N/A void prefetchw (LIR_Opr src);

0N/A

0N/A void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);

0N/A void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest);

0N/A

0N/A void move_regs(Register from_reg, Register to_reg);

0N/A void swap_reg(Register a, Register b);

0N/A

0N/A void emit_op0(LIR_Op0* op);

0N/A void emit_op1(LIR_Op1* op);

0N/A void emit_op2(LIR_Op2* op);

0N/A void emit_op3(LIR_Op3* op);

0N/A void emit_opBranch(LIR_OpBranch* op);

0N/A void emit_opLabel(LIR_OpLabel* op);

0N/A void emit_arraycopy(LIR_OpArrayCopy* op);

0N/A void emit_opConvert(LIR_OpConvert* op);

0N/A void emit_alloc_obj(LIR_OpAllocObj* op);

0N/A void emit_alloc_array(LIR_OpAllocArray* op);

0N/A void emit_opTypeCheck(LIR_OpTypeCheck* op);

1711N/A void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null);

0N/A void emit_compare_and_swap(LIR_OpCompareAndSwap* op);

0N/A void emit_lock(LIR_OpLock* op);

0N/A void emit_call(LIR_OpJavaCall* op);

0N/A void emit_rtcall(LIR_OpRTCall* op);

0N/A void emit_profile_call(LIR_OpProfileCall* op);

0N/A void emit_delay(LIR_OpDelay* op);

0N/A

0N/A void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);

0N/A void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);

0N/A void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);

0N/A

0N/A void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);

0N/A

0N/A void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);

0N/A void move_op(LIR_Opr src, LIR_Opr result, BasicType type,

1909N/A LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide);

0N/A void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);

0N/A void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions

0N/A void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);

1977N/A void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);

0N/A

1295N/A void call( LIR_OpJavaCall* op, relocInfo::relocType rtype);

1295N/A void ic_call( LIR_OpJavaCall* op);

1295N/A void vtable_call( LIR_OpJavaCall* op);

1295N/A

0N/A void osr_entry();

0N/A

0N/A void build_frame();

0N/A

1378N/A void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info);

1378N/A void unwind_op(LIR_Opr exceptionOop);

0N/A void monitor_address(int monitor_ix, LIR_Opr dst);

0N/A

0N/A void align_backward_branch_target();

0N/A void align_call(LIR_Code code);

0N/A

0N/A void negate(LIR_Opr left, LIR_Opr dest);

0N/A void leal(LIR_Opr left, LIR_Opr dest);

0N/A

0N/A void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);

0N/A

0N/A void membar();

0N/A void membar_acquire();

0N/A void membar_release();

3452N/A void membar_loadload();

3452N/A void membar_storestore();

3452N/A void membar_loadstore();

3452N/A void membar_storeload();

0N/A void get_thread(LIR_Opr result);

0N/A

0N/A void verify_oop_map(CodeEmitInfo* info);

0N/A

4015N/A void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp);

4015N/A

1879N/A#ifdef TARGET_ARCH_x86

1879N/A# include "c1_LIRAssembler_x86.hpp"

1879N/A#endif

1879N/A#ifdef TARGET_ARCH_sparc

1879N/A# include "c1_LIRAssembler_sparc.hpp"

1879N/A#endif

2073N/A#ifdef TARGET_ARCH_arm

2073N/A# include "c1_LIRAssembler_arm.hpp"

2073N/A#endif

2073N/A#ifdef TARGET_ARCH_ppc

2073N/A# include "c1_LIRAssembler_ppc.hpp"

2073N/A#endif

1879N/A

0N/A};

1879N/A

1879N/A#endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP