Searched defs:reg (Results 1 - 21 of 21) sorted by relevance

/solaris-x11-s12/open-src/kernel/i915/src/
H A Di915_ums.c54 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); local
62 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
70 array[i] = I915_READ(reg + (i << 2));
76 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); local
84 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
92 I915_WRITE(reg + (i << 2), array[i]);
H A Di915_suspend.c37 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) argument
41 I915_WRITE8(index_port, reg);
45 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) argument
50 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
54 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) argument
59 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
63 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) argument
67 I915_WRITE8(index_port, reg);
H A Dintel_sideband.c104 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg) argument
109 DPIO_OPCODE_REG_READ, reg, &val);
114 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) argument
117 DPIO_OPCODE_REG_WRITE, reg, &val);
121 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, argument
133 I915_WRITE(SBI_ADDR, (reg << 16));
150 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, argument
163 I915_WRITE(SBI_ADDR, (reg << 16));
H A Di915_gem_context.c114 u32 reg; local
118 reg = I915_READ(CXT_SIZE);
119 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
122 reg = I915_READ(GEN7_CXT_SIZE);
126 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
H A Dintel_i2c.c43 int reg; member in struct:gmbus_port
209 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
H A Dintel_lvds.c53 u32 reg; member in struct:intel_lvds_encoder
76 tmp = I915_READ(lvds_encoder->reg);
136 temp = I915_READ(lvds_encoder->reg);
168 * only controlled through the PIPECONF reg. */
184 I915_WRITE(lvds_encoder->reg, temp);
206 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
209 POSTING_READ(lvds_encoder->reg);
237 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg)
[all...]
H A Dintel_panel.c529 uint32_t reg, tmp; local
531 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
533 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
563 uint32_t reg, tmp; local
565 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
568 tmp = I915_READ(reg);
587 I915_WRITE(reg, tmp);
588 POSTING_READ(reg);
589 I915_WRITE(reg, tm
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H A Dintel_sprite.c506 int reg = DSPCNTR(intel_crtc->plane); local
514 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
523 int reg = DSPCNTR(intel_crtc->plane); local
528 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
H A Dintel_ddi.c94 u32 reg; local
108 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
109 I915_WRITE(reg, ddi_translations[i]);
110 reg += 4;
149 uint32_t reg = DDI_BUF_CTL(port); local
154 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
643 uint32_t reg, val; local
679 reg = WRPLL_CTL1;
685 reg = WRPLL_CTL2;
692 if(I915_READ(reg)
853 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); local
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H A Dintel_hdmi.c151 DRM_ERROR("Writing DIP with CTL reg disabled\n");
186 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); local
188 u32 val = I915_READ(reg);
191 DRM_ERROR("Writing DIP with CTL reg disabled\n");
198 I915_WRITE(reg, val);
214 I915_WRITE(reg, val);
215 POSTING_READ(reg);
226 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); local
228 u32 val = I915_READ(reg);
231 DRM_ERROR("Writing DIP with CTL reg disable
269 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); local
391 u32 reg = VIDEO_DIP_CTL; local
456 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); local
516 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); local
551 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); local
585 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); local
[all...]
H A Dintel_ringbuffer.h230 int reg)
233 return regs[reg];
238 int reg, u32 value)
241 regs[reg] = value;
229 intel_read_status_page(struct intel_ring_buffer *ring, int reg) argument
237 intel_write_status_page(struct intel_ring_buffer *ring, int reg, u32 value) argument
H A Di915_gem_debug.c56 uint32_t reg; member in struct:instdone_bit
65 add_instdone_bit(uint32_t reg, uint32_t bit, const char *name) argument
67 instdone_bits[num_instdone_bits].reg = reg;
361 #define ring_read(ring, reg) I915_READ(ring->mmio + reg)
453 if (top_bit->bit->reg == INST_DONE_1)
H A Dintel_ringbuffer.c975 u32 reg = RING_INSTPM(ring->mmio_base); local
976 I915_WRITE(reg,
979 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
H A Di915_dma.c71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) argument
75 return regs[reg];
77 return intel_read_status_page(LP_RING(dev_priv), reg);
80 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
H A Di915_drv.c782 * - reset the chip using the reset reg
1183 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1185 ((reg) < 0x40000) && \
1186 ((reg) != FORCEWAKE))
1198 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) argument
1203 reg);
1209 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) argument
1213 DRM_INFO("Unclaimed write to %x\n", reg);
1218 u8 i915_read8(struct drm_i915_private *dev_priv, u32 reg) argument
1225 if (NEEDS_FORCE_WAKE(dev_priv, reg)) {
1239 i915_read16(struct drm_i915_private *dev_priv, u32 reg) argument
1260 i915_read32(struct drm_i915_private *dev_priv, u32 reg) argument
1281 i915_read64(struct drm_i915_private *dev_priv, u32 reg) argument
1302 i915_write8(struct drm_i915_private *dev_priv, u32 reg, u8 val) argument
1324 i915_write16(struct drm_i915_private *dev_priv, u32 reg, u16 val) argument
1346 i915_write32(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
1368 i915_write64(struct drm_i915_private *dev_priv, u32 reg, u64 val) argument
1420 struct drm_i915_reg_read *reg = data; local
[all...]
H A Di915_irq.c320 u32 reg = PIPESTAT(pipe); local
321 u32 pipestat = I915_READ(reg) & 0x7fff0000;
328 I915_WRITE(reg, pipestat);
329 POSTING_READ(reg);
335 u32 reg = PIPESTAT(pipe); local
336 u32 pipestat = I915_READ(reg) & 0x7fff0000;
342 I915_WRITE(reg, pipestat);
343 POSTING_READ(reg);
409 int reg = PIPE_FRMCOUNT_GM45(pipe); local
417 return I915_READ(reg);
942 int reg = PIPESTAT(pipe); local
3008 int reg = PIPESTAT(pipe); local
3181 int reg = PIPESTAT(pipe); local
3414 int reg = PIPESTAT(pipe); local
[all...]
H A Dintel_dp.c193 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
2427 uint8_t reg; local
2429 &reg, 1))
2431 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
H A Di915_gem.c50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
1428 struct drm_i915_fence_reg *reg; local
1430 reg = &dev_priv->fence_regs[obj->fence_reg];
1431 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list, (caddr_t)reg);
1784 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; local
1790 if (reg->obj) {
1791 i915_gem_object_update_fence(reg->obj, reg,
1792 reg
2181 i965_write_fence_reg(struct drm_device *dev, int reg, struct drm_i915_gem_object *obj) argument
2233 i915_write_fence_reg(struct drm_device *dev, int reg, struct drm_i915_gem_object *obj) argument
2277 i830_write_fence_reg(struct drm_device *dev, int reg, struct drm_i915_gem_object *obj) argument
2314 i915_gem_write_fence(struct drm_device *dev, int reg, struct drm_i915_gem_object *obj) argument
2357 int reg = fence_number(dev_priv, fence); local
2414 struct drm_i915_fence_reg *reg, *avail; local
2462 struct drm_i915_fence_reg *reg; local
[all...]
H A Dintel_sdvo.c1258 /* done in crtc_mode_set as the dpll_md reg must be written early */
2245 struct intel_sdvo *sdvo, u32 reg)
2262 struct intel_sdvo *sdvo, u32 reg)
2244 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, struct intel_sdvo *sdvo, u32 reg) argument
2261 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, struct intel_sdvo *sdvo, u32 reg) argument
H A Dintel_pm.c1098 u32 reg; local
1118 reg = I915_READ(DSPFW1);
1119 reg &= ~DSPFW_SR_MASK;
1120 reg |= wm << DSPFW_SR_SHIFT;
1121 I915_WRITE(DSPFW1, reg);
1122 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1128 reg = I915_READ(DSPFW3);
1129 reg &= ~DSPFW_CURSOR_SR_MASK;
1130 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1131 I915_WRITE(DSPFW3, reg);
2738 int sprite_wm, reg; local
4144 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); local
[all...]
H A Dintel_display.c813 int reg = PIPECONF(cpu_transcoder); local
816 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 int reg = PIPEDSL(pipe); local
831 last_line = I915_READ(reg) & line_mask;
833 } while (((I915_READ(reg) & line_mask) != last_line) &&
894 int reg; local
898 reg = DPLL(pipe);
899 val = I915_READ(reg);
948 int reg; local
956 reg
974 int reg; local
991 int reg; local
1011 int reg; local
1052 int reg; local
1079 int reg; local
1098 int reg, i; local
1128 int reg, i; local
1174 int reg; local
1251 assert_pch_dp_disabled(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 port_sel) argument
1264 assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) argument
1280 int reg; local
1319 int reg; local
1358 int reg; local
1471 uint32_t reg, val, pipeconf_val; local
1556 uint32_t reg, val; local
1619 int reg; local
1673 int reg; local
1720 int reg; local
1747 int reg; local
1880 u32 reg; local
1980 u32 reg; local
2229 u32 reg, temp; local
2303 u32 reg, temp, tries; local
2404 u32 reg, temp, i, retry; local
2536 u32 reg, temp, i; local
2651 u32 reg, temp; local
2688 u32 reg, temp; local
2718 u32 reg, temp; local
2931 u32 reg, temp; local
3395 u32 reg, temp; local
8874 uint32_t reg, val; local
8892 uint32_t reg, val; local
9714 u32 reg, val; local
9733 u32 reg; local
[all...]

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