Cross Reference: /solaris-x11-s12/open-src/kernel/i915/src/intel

Lines Matching defs:reg
813 		int reg = PIPECONF(cpu_transcoder);
816 		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 		int reg = PIPEDSL(pipe);
831 			last_line = I915_READ(reg) & line_mask;
833 		} while (((I915_READ(reg) & line_mask) != last_line) &&
894 	int reg;
898 	reg = DPLL(pipe);
899 	val = I915_READ(reg);
948 	int reg;
956 		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
957 		val = I915_READ(reg);
960 	reg = FDI_TX_CTL(pipe);
961 	val = I915_READ(reg);
974 	int reg;
978 	reg = FDI_RX_CTL(pipe);
979 	val = I915_READ(reg);
991 	int reg;
1002 	reg = FDI_TX_CTL(pipe);
1003 	val = I915_READ(reg);
1011 	int reg;
1014 	reg = FDI_RX_CTL(pipe);
1015 	val = I915_READ(reg);
1052 	int reg;
1066 		reg = PIPECONF(cpu_transcoder);
1067 		val = I915_READ(reg);
1079 	int reg;
1083 	reg = DSPCNTR(plane);
1084 	val = I915_READ(reg);
1098 	int reg, i;
1104 		reg = DSPCNTR(pipe);
1105 		val = I915_READ(reg);
1114 		reg = DSPCNTR(i);
1115 		val = I915_READ(reg);
1128 	int reg, i;
1133 			reg = SPCNTR(pipe, i);
1134 			val = I915_READ(reg);
1140 		reg = SPRCTL(pipe);
1141 		val = I915_READ(reg);
1146 		reg = DVSCNTR(pipe);
1147 		val = I915_READ(reg);
1174 	int reg;
1178 	reg = PCH_TRANSCONF(pipe);
1179 	val = I915_READ(reg);
1252 				   enum pipe pipe, int reg, u32 port_sel)
1254 	u32 val = I915_READ(reg);
1257 			reg, pipe_name(pipe));
1265 				     enum pipe pipe, int reg)
1267 	u32 val = I915_READ(reg);
1270 			reg, pipe_name(pipe));
1280 	int reg;
1287 	reg = PCH_ADPA;
1288 	val = I915_READ(reg);
1293 	reg = PCH_LVDS;
1294 	val = I915_READ(reg);
1310  * make sure the PLL reg is writable first though, since the panel write
1319 	int reg;
1331 	reg = DPLL(pipe);
1332 	val = I915_READ(reg);
1336 	I915_WRITE(reg, val);
1337 	POSTING_READ(reg);
1339 	I915_WRITE(reg, val);
1340 	POSTING_READ(reg);
1342 	I915_WRITE(reg, val);
1343 	POSTING_READ(reg);
1358 	int reg;
1368 	reg = DPLL(pipe);
1369 	val = I915_READ(reg);
1371 	I915_WRITE(reg, val);
1372 	POSTING_READ(reg);
1471 	uint32_t reg, val, pipeconf_val;
1487 		reg = TRANS_CHICKEN2(pipe);
1488 		val = I915_READ(reg);
1490 		I915_WRITE(reg, val);
1493 	reg = PCH_TRANSCONF(pipe);
1494 	val = I915_READ(reg);
1500 		 * that in pipeconf reg.
1516 	I915_WRITE(reg, val | TRANS_ENABLE);
1517 	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1556 	uint32_t reg, val;
1565 	reg = PCH_TRANSCONF(pipe);
1566 	val = I915_READ(reg);
1568 	I915_WRITE(reg, val);
1570 	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1575 		reg = TRANS_CHICKEN2(pipe);
1576 		val = I915_READ(reg);
1578 		I915_WRITE(reg, val);
1619 	int reg;
1647 	reg = PIPECONF(cpu_transcoder);
1648 	val = I915_READ(reg);
1652 	I915_WRITE(reg, val | PIPECONF_ENABLE);
1673 	int reg;
1687 	reg = PIPECONF(cpu_transcoder);
1688 	val = I915_READ(reg);
1692 	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1698  * trigger in order to latch.  The display address reg provides this.
1720 	int reg;
1726 	reg = DSPCNTR(plane);
1727 	val = I915_READ(reg);
1731 	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1747 	int reg;
1750 	reg = DSPCNTR(plane);
1751 	val = I915_READ(reg);
1755 	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1880 	u32 reg;
1894 	reg = DSPCNTR(plane);
1895 	dspcntr = I915_READ(reg);
1940 	I915_WRITE(reg, dspcntr);
1964 	POSTING_READ(reg);
1980 	u32 reg;
1995 	reg = DSPCNTR(plane);
1996 	dspcntr = I915_READ(reg);
2035 	I915_WRITE(reg, dspcntr);
2055 	POSTING_READ(reg);
2229 	u32 reg, temp;
2232 	reg = FDI_TX_CTL(pipe);
2233 	temp = I915_READ(reg);
2241 	I915_WRITE(reg, temp);
2243 	reg = FDI_RX_CTL(pipe);
2244 	temp = I915_READ(reg);
2252 	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2255 	POSTING_READ(reg);
2260 		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2303 	u32 reg, temp, tries;
2311 	reg = FDI_RX_IMR(pipe);
2312 	temp = I915_READ(reg);
2315 	I915_WRITE(reg, temp);
2316 	POSTING_READ(reg);
2320 	reg = FDI_TX_CTL(pipe);
2321 	temp = I915_READ(reg);
2326 	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2328 	reg = FDI_RX_CTL(pipe);
2329 	temp = I915_READ(reg);
2332 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
2334 	POSTING_READ(reg);
2342 	reg = FDI_RX_IIR(pipe);
2344 		temp = I915_READ(reg);
2349 			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2357 	reg = FDI_TX_CTL(pipe);
2358 	temp = I915_READ(reg);
2361 	I915_WRITE(reg, temp);
2363 	reg = FDI_RX_CTL(pipe);
2364 	temp = I915_READ(reg);
2367 	I915_WRITE(reg, temp);
2369 	POSTING_READ(reg);
2372 	reg = FDI_RX_IIR(pipe);
2374 		temp = I915_READ(reg);
2378 			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2404 	u32 reg, temp, i, retry;
2408 	reg = FDI_RX_IMR(pipe);
2409 	temp = I915_READ(reg);
2412 	I915_WRITE(reg, temp);
2414 	POSTING_READ(reg);
2418 	reg = FDI_TX_CTL(pipe);
2419 	temp = I915_READ(reg);
2427 	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2432 	reg = FDI_RX_CTL(pipe);
2433 	temp = I915_READ(reg);
2441 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
2443 	POSTING_READ(reg);
2447 		reg = FDI_TX_CTL(pipe);
2448 		temp = I915_READ(reg);
2451 		I915_WRITE(reg, temp);
2453 		POSTING_READ(reg);
2457 			reg = FDI_RX_IIR(pipe);
2458 			temp = I915_READ(reg);
2461 				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2474 	reg = FDI_TX_CTL(pipe);
2475 	temp = I915_READ(reg);
2483 	I915_WRITE(reg, temp);
2485 	reg = FDI_RX_CTL(pipe);
2486 	temp = I915_READ(reg);
2494 	I915_WRITE(reg, temp);
2496 	POSTING_READ(reg);
2500 		reg = FDI_TX_CTL(pipe);
2501 		temp = I915_READ(reg);
2504 		I915_WRITE(reg, temp);
2506 		POSTING_READ(reg);
2510 			reg = FDI_RX_IIR(pipe);
2511 			temp = I915_READ(reg);
2514 				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2536 	u32 reg, temp, i;
2540 	reg = FDI_RX_IMR(pipe);
2541 	temp = I915_READ(reg);
2544 	I915_WRITE(reg, temp);
2546 	POSTING_READ(reg);
2553 	reg = FDI_TX_CTL(pipe);
2554 	temp = I915_READ(reg);
2562 	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2567 	reg = FDI_RX_CTL(pipe);
2568 	temp = I915_READ(reg);
2573 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
2575 	POSTING_READ(reg);
2579 		reg = FDI_TX_CTL(pipe);
2580 		temp = I915_READ(reg);
2583 		I915_WRITE(reg, temp);
2585 		POSTING_READ(reg);
2588 		reg = FDI_RX_IIR(pipe);
2589 		temp = I915_READ(reg);
2593 		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2594 			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2603 	reg = FDI_TX_CTL(pipe);
2604 	temp = I915_READ(reg);
2609 	I915_WRITE(reg, temp);
2611 	reg = FDI_RX_CTL(pipe);
2612 	temp = I915_READ(reg);
2615 	I915_WRITE(reg, temp);
2617 	POSTING_READ(reg);
2621 		reg = FDI_TX_CTL(pipe);
2622 		temp = I915_READ(reg);
2625 		I915_WRITE(reg, temp);
2627 		POSTING_READ(reg);
2630 		reg = FDI_RX_IIR(pipe);
2631 		temp = I915_READ(reg);
2635 			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2651 	u32 reg, temp;
2655 	reg = FDI_RX_CTL(pipe);
2656 	temp = I915_READ(reg);
2660 	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2662 	POSTING_READ(reg);
2666 	temp = I915_READ(reg);
2667 	I915_WRITE(reg, temp | FDI_PCDCLK);
2669 	POSTING_READ(reg);
2673 	reg = FDI_TX_CTL(pipe);
2674 	temp = I915_READ(reg);
2676 		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2678 		POSTING_READ(reg);
2688 	u32 reg, temp;
2691 	reg = FDI_RX_CTL(pipe);
2692 	temp = I915_READ(reg);
2693 	I915_WRITE(reg, temp & ~FDI_PCDCLK);
2696 	reg = FDI_TX_CTL(pipe);
2697 	temp = I915_READ(reg);
2698 	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2700 	POSTING_READ(reg);
2703 	reg = FDI_RX_CTL(pipe);
2704 	temp = I915_READ(reg);
2705 	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2708 	POSTING_READ(reg);
2718 	u32 reg, temp;
2721 	reg = FDI_TX_CTL(pipe);
2722 	temp = I915_READ(reg);
2723 	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2724 	POSTING_READ(reg);
2726 	reg = FDI_RX_CTL(pipe);
2727 	temp = I915_READ(reg);
2730 	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2732 	POSTING_READ(reg);
2741 	reg = FDI_TX_CTL(pipe);
2742 	temp = I915_READ(reg);
2745 	I915_WRITE(reg, temp);
2747 	reg = FDI_RX_CTL(pipe);
2748 	temp = I915_READ(reg);
2759 	I915_WRITE(reg, temp);
2761 	POSTING_READ(reg);
2931 	u32 reg, temp;
2976 		reg = TRANS_DP_CTL(pipe);
2977 		temp = I915_READ(reg);
3004 		I915_WRITE(reg, temp);
3395 	u32 reg, temp;
3433 			reg = TRANS_DP_CTL(pipe);
3434 			temp = I915_READ(reg);
3438 			I915_WRITE(reg, temp);
8874 	uint32_t reg, val;
8879 	reg = PCH_DPLL(pll->id);
8880 	val = I915_READ(reg);
8882 	I915_WRITE(reg, val);
8883 	POSTING_READ(reg);
8892 	uint32_t reg, val;
8900 	reg = PCH_DPLL(pll->id);
8901 	val = I915_READ(reg);
8903 	I915_WRITE(reg, val);
8904 	POSTING_READ(reg);
9714 	u32 reg, val;
9719 	reg = DSPCNTR(!crtc->plane);
9720 	val = I915_READ(reg);
9733 	u32 reg;
9736 	reg = PIPECONF(crtc->config.cpu_transcoder);
9737 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);