/*
*/
/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
*/
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* Copyright (c) 2009, 2012, Intel Corporation.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "intel_drv.h"
[HPD_CRT] = SDE_CRT_HOTPLUG,
};
};
};
};
};
/* For display hotplug interrupt */
static void
{
}
}
static void
{
}
}
{
return false;
}
return true;
}
{
return false;
}
return true;
}
{
if (enable)
else
}
bool enable)
{
if (enable) {
if (!ivb_can_enable_err_int(dev))
return;
} else {
}
}
bool enable)
{
if (enable)
else
}
enum transcoder pch_transcoder,
bool enable)
{
if (enable) {
if (!cpt_can_enable_serr_int(dev))
return;
} else {
}
}
/**
* @dev: drm device
* @pipe: pipe
* @enable: true if we want to report FIFO underrun errors, false otherwise
*
* This function makes us disable or enable CPU fifo underruns for a specific
* pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
* reporting for one pipe may also disable all the other CPU error interruts for
* bit for all the pipes.
*
* Returns the previous state of underrun reporting.
*/
{
unsigned long flags;
bool ret;
goto done;
done:
return ret;
}
/**
* @dev: drm device
* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
* @enable: true if we want to report FIFO underrun errors, false otherwise
*
* This function makes us disable or enable PCH fifo underruns for a specific
* underrun reporting for one transcoder may also disable all the other PCH
* error interruts for the other transcoders, due to the fact that there's just
*
* Returns the previous state of underrun reporting.
*/
enum transcoder pch_transcoder,
bool enable)
{
enum pipe p;
unsigned long flags;
bool ret;
if (HAS_PCH_LPT(dev)) {
for_each_pipe(p) {
if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
crtc = c;
break;
}
}
if (!crtc) {
DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
return false;
}
} else {
}
goto done;
if (HAS_PCH_IBX(dev))
else
done:
return ret;
}
void
{
return;
/* Enable the interrupt, clear any pending status */
}
void
{
return;
}
/**
* i915_pipe_enabled - check if a pipe is enabled
* @dev: DRM device
* @pipe: pipe to check
*
* Reading certain registers when the pipe is disabled can hang the chip.
* Use this routine to make sure the PLL is running and the pipe is active
* before reading such registers if unsure.
*/
static int
{
/* Locking is horribly broken here, but whatever. */
return intel_crtc->active;
} else {
}
}
/* Called from drm generic code, passed a 'crtc', which
* we use as a pipe index
*/
{
unsigned long high_frame;
unsigned long low_frame;
DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
return 0;
}
/*
* High & low register fields aren't synchronized, so make sure
* we get a low value that's stable across two reads of the high
* register.
*/
do {
}
{
DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
return 0;
}
}
{
bool in_vbl = true;
int ret = 0;
pipe);
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
return 0;
}
/* Get vtotal. */
/* No obvious pixelcount register. Only query vertical
* scanout position from Display scan line register.
*/
/* Decode into vertical scanout position. Don't have
* horizontal scanout position.
*/
*hpos = 0;
} else {
/* Have access to pixelcount since start of frame.
* We can split this into vertical and horizontal
* scanout position.
*/
}
/* Query vblank area. */
/* Test position against vblank region. */
in_vbl = false;
/* Inside "upper part" of vblank area? Apply corrective offset: */
/* Readouts valid? */
if (vbl > 0)
/* In vblank? */
if (in_vbl)
return ret;
}
int *max_error,
struct timeval *vblank_time,
unsigned flags)
{
return -EINVAL;
}
/* Get drm_crtc to timestamp: */
return -EINVAL;
}
return -EBUSY;
}
/* Helper routine in DRM core does all the work: */
crtc);
}
{
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
}
/*
* Handle hotplug events outside the interrupt handler proper.
*/
{
unsigned long irqflags;
bool hpd_disabled = false;
bool changed = false;
/* HPD irq before everything is fully set up. */
return;
DRM_DEBUG_KMS("running encoder hotplug functions\n");
dev_priv->hpd_event_bits = 0;
DRM_INFO("HPD interrupt storm detected on connector %s: "
"switching from hotplug detection to polling\n",
hpd_disabled = true;
}
DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
}
}
/* if there were no outputs to poll, poll was disabled,
* therefore make sure it's enabled when disabling HPD on
* some connectors */
if (hpd_disabled) {
}
if (intel_encoder->hot_plug)
changed = true;
}
}
if (changed)
}
{
unsigned long flags;
/* Handle RCS change request from hw */
}
return;
}
struct intel_ring_buffer *ring)
{
return;
}
}
{
if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
return;
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
/*
* For better performance, jump directly
* to RPe if we're below it.
*/
} else
/* sysfs frequency interfaces may have snuck in while servicing the
* interrupt
*/
else
}
}
/**
* ivybridge_parity_work - Workqueue called when a parity error interrupt
* occurred.
* @work: workqueue struct
*
* Doesn't actually do anything except notify userspace. As a consequence of
* this event, userspace should try to remap the bad rows since statistically
* it is likely the same row is more likely to go bad again.
*/
{
unsigned long flags;
/* We must turn off DOP level clock gating to access the L3 registers.
* any time we access those registers.
*/
DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
}
{
unsigned long flags;
if (!HAS_L3_GPU_CACHE(dev))
return;
}
struct drm_i915_private *dev_priv,
{
if (gt_iir &
if (gt_iir & GT_BSD_USER_INTERRUPT)
if (gt_iir & GT_BLT_USER_INTERRUPT)
if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
i915_handle_error(dev, false);
}
}
{
unsigned long flags;
/*
* IIR bits should never already be set because IMR should
* prevent an interrupt from being shown in IIR. The warning
* displays a case where we've unsafely cleared
* dev_priv->rps.pm_iir. Although missing an interrupt of the same
* type is not a problem, it displays a problem in the logic.
*
* The mask bit in IMR is cleared by dev_priv->rps.work.
*/
}
{
int i;
bool storm_detected = false;
if (!hotplug_trigger)
return;
for (i = 1; i < HPD_NUM_PINS; i++) {
if (!(hpd[i] & hotplug_trigger) ||
continue;
DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
storm_detected = true;
} else {
}
}
if (storm_detected)
&dev_priv->hotplug_work);
}
{
}
{
}
/* Unlike gen6_queue_rps_work() from which this function is originally derived,
* we must be able to deal with other PM interrupts. This is complicated because
* of the way in which we use the masks to defer the RPS work (which for
* posterity is necessary because of forcewake).
*/
{
unsigned long flags;
/* never want to mask useful interrupts. (also posting read) */
/* TODO: if queue_work is slow, move it out of the spinlock */
}
if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
if (pm_iir & PM_VEBOX_USER_INTERRUPT)
if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
}
}
}
{
/* LINTED */
unsigned long irqflags;
int pipe;
while (true) {
goto out;
ret = IRQ_HANDLED;
/*
* Clear the PIPE*STAT regs before the IIR
*/
DRM_DEBUG_DRIVER("pipe %c underrun\n",
}
}
}
}
/* Consume port. Then clear IIR or we'll miss events */
if (iir & I915_DISPLAY_PORT_INTERRUPT) {
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
}
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
if (pm_iir & GEN6_PM_RPS_EVENTS)
}
out:
return ret;
}
{
int pipe;
if (pch_iir & SDE_AUDIO_POWER_MASK) {
DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
}
if (pch_iir & SDE_AUX_MASK)
if (pch_iir & SDE_AUDIO_HDCP_MASK)
DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
if (pch_iir & SDE_AUDIO_TRANS_MASK)
DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
if (pch_iir & SDE_POISON)
DRM_ERROR("PCH poison interrupt\n");
if (pch_iir & SDE_FDI_MASK)
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
false))
DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
false))
DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
}
{
if (err_int & ERR_INT_POISON)
DRM_ERROR("Poison interrupt\n");
if (err_int & ERR_INT_FIFO_UNDERRUN_A)
DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
if (err_int & ERR_INT_FIFO_UNDERRUN_B)
DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
if (err_int & ERR_INT_FIFO_UNDERRUN_C)
DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
}
{
if (serr_int & SERR_INT_POISON)
DRM_ERROR("PCH poison interrupt\n");
false))
DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
false))
DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
false))
DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
}
{
int pipe;
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
}
if (pch_iir & SDE_AUX_MASK_CPT)
if (pch_iir & SDE_GMBUS_CPT)
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
if (pch_iir & SDE_FDI_MASK_CPT)
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
if (pch_iir & SDE_ERROR_CPT)
}
{
/* LINTED */
int i;
/* We get interrupts on unclaimed registers, so check for this before we
* do any I915_{READ,WRITE}. */
if (IS_HASWELL(dev) &&
DRM_ERROR("Unclaimed register before interrupt\n");
}
/* disable master interrupt before clearing iir */
/* Disable south interrupts. We'll only write to SDEIIR once, so further
* interrupts will will be stored on its back queue, and then we'll be
* able to process them after we restore SDEIER (as soon as we restore
* it, we'll get an interrupt if SDEIIR still has something to process
* due to its back queue). */
if (!HAS_PCH_NOP(dev)) {
I915_WRITE(SDEIER, 0);
}
/* On Haswell, also mask ERR_INT because we don't want to risk
* generating "unclaimed register" interrupts from inside the interrupt
* handler. */
if (IS_HASWELL(dev)) {
}
if (gt_iir) {
ret = IRQ_HANDLED;
}
if (de_iir) {
if (de_iir & DE_ERR_INT_IVB)
if (de_iir & DE_AUX_CHANNEL_A_IVB)
for (i = 0; i < 3; i++) {
drm_handle_vblank(dev, i);
}
}
/* check event from PCH */
/* clear PCH hotplug event before clear CPU irq */
}
ret = IRQ_HANDLED;
}
if (pm_iir) {
if (IS_HASWELL(dev))
else if (pm_iir & GEN6_PM_RPS_EVENTS)
ret = IRQ_HANDLED;
}
if (IS_HASWELL(dev)) {
if (ivb_can_enable_err_int(dev))
}
if (!HAS_PCH_NOP(dev)) {
}
return ret;
}
struct drm_i915_private *dev_priv,
{
if (gt_iir &
if (gt_iir & ILK_BSD_USER_INTERRUPT)
}
{
/* disable master interrupt before clearing iir */
/* Disable south interrupts. We'll only write to SDEIIR once, so further
* interrupts will will be stored on its back queue, and then we'll be
* able to process them after we restore SDEIER (as soon as we restore
* it, we'll get an interrupt if SDEIIR still has something to process
* due to its back queue). */
I915_WRITE(SDEIER, 0);
goto done;
ret = IRQ_HANDLED;
else
if (de_iir & DE_AUX_CHANNEL_A)
if (de_iir & DE_PIPEA_VBLANK)
drm_handle_vblank(dev, 0);
if (de_iir & DE_PIPEB_VBLANK)
DRM_ERROR("Poison interrupt\n");
if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
if (de_iir & DE_PLANEA_FLIP_DONE) {
}
if (de_iir & DE_PLANEB_FLIP_DONE) {
}
/* check event from PCH */
if (de_iir & DE_PCH_EVENT) {
if (HAS_PCH_CPT(dev))
else
/* should clear PCH hotplug event before clear CPU irq */
}
done:
return ret;
}
/**
* i915_error_work_func - do process context error handling work
* @work: work struct
*
* Fire an error uevent so userspace can see that a hang or error
* was detected.
*/
{
work);
/* LINTED */
/* LINTED */
/* LINTED */
int i, ret;
DRM_DEBUG_DRIVER("generating error event\n");
/* OSOL_i915: kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */
/*
* Note that there's only one work item which does gpu resets, so we
* need not worry about concurrent gpu resets potentially incrementing
* error->reset_counter twice. We only need to take care of another
* quick check for that is good enough: schedule_work ensures the
* correct ordering between hang detection and this work item, and since
* the reset in-progress bit is only ever set by code outside of this
* work we don't need to worry about any other races.
*/
DRM_DEBUG_DRIVER("resetting chip\n");
/* OSOL_i915: kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */
if (ret == 0) {
/*
* After all the gem state is reset, increment the reset
* counter and wake up everyone waiting for the reset to
* complete.
*
* Since unlock operations are a one-sided barrier only,
* we need to insert a barrier here to order any seqno
* updates before
* the counter increment.
*/
if (gpu_dump > 0) {
}
} else {
}
DRM_INFO("resetting done");
}
}
/* NB: please notice the memset */
{
case 2:
case 3:
break;
case 4:
case 5:
case 6:
break;
default:
DRM_INFO("Unsupported platform\n");
case 7:
break;
}
}
#ifdef CONFIG_DEBUG_FS
static struct drm_i915_error_object *
struct drm_i915_gem_object *src,
const int num_pages)
{
int i;
return NULL;
return NULL;
for (i = 0; i < num_pages; i++) {
unsigned long flags;
void *d;
if (d == NULL)
goto unwind;
void __iomem *s;
/* Simply ignore tiling or any overlapping fence.
* It's part of the error state, and this hopefully
* captures what the GPU read.
*/
memcpy_fromio(d, s, PAGE_SIZE);
unsigned long offset;
offset += i << PAGE_SHIFT;
} else {
void *s;
s = kmap_atomic(page);
kunmap_atomic(s);
}
}
return dst;
while (i--)
return NULL;
}
static void
{
int page;
return;
}
void
{
int i;
}
}
struct drm_i915_gem_object *obj)
{
if (obj->user_pin_count > 0)
}
{
int i = 0;
if (++i == count)
break;
}
return i;
}
{
int i = 0;
continue;
if (++i == count)
break;
}
return i;
}
struct drm_i915_error_state *error)
{
int i;
/* Fences */
case 7:
case 6:
for (i = 0; i < dev_priv->num_fence_regs; i++)
break;
case 5:
case 4:
for (i = 0; i < 16; i++)
break;
case 3:
for (i = 0; i < 8; i++)
case 2:
for (i = 0; i < 8; i++)
break;
default:
BUG();
}
}
static struct drm_i915_error_object *
struct intel_ring_buffer *ring)
{
return NULL;
return NULL;
}
continue;
continue;
continue;
/* We need to copy these to an anonymous buffer as the simplest
* method to avoid being overwritten by userspace.
*/
}
return NULL;
}
struct drm_i915_error_state *error,
struct intel_ring_buffer *ring)
{
}
} else {
}
}
struct drm_i915_error_state *error,
struct drm_i915_error_ring *ering)
{
/* Currently render ring is the only HW context user */
return;
obj, 1);
}
}
}
struct drm_i915_error_state *error)
{
int i, count;
count = 0;
count++;
continue;
}
count = 0;
}
}
}
/**
* i915_capture_error_state - capture an error record for later analysis
* @dev: drm device
*
* Should be called when an error is detected (either a hang or an error
* interrupt) to capture error state from the time of the error. Fills
* out a structure which becomes available in debugfs for user level tools
* to pick up.
*/
{
unsigned long flags;
int i, pipe;
if (error)
return;
/* Account for pipe specific data like PIPE*STAT */
if (!error) {
DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
return;
}
DRM_INFO("capturing error event; look for more information in "
if (HAS_HW_CONTEXTS(dev))
if (HAS_PCH_SPLIT(dev))
else if (IS_VALLEYVIEW(dev))
else
if (IS_VALLEYVIEW(dev))
if (!HAS_PCH_SPLIT(dev))
}
/* Record buffers on the active and pinned lists. */
i = 0;
i++;
error->active_bo_count = i;
i++;
if (i) {
}
}
if (error)
}
{
unsigned long flags;
if (error)
}
#else
#define i915_capture_error_state(x)
#endif
{
int pipe;
if (!eir)
return;
DRM_DEBUG(" IPEIR: 0x%08x\n",
DRM_DEBUG(" IPEHR: 0x%08x\n",
DRM_DEBUG(" INSTDONE: 0x%08x\n",
DRM_DEBUG(" INSTPS: 0x%08x\n",
DRM_DEBUG(" INSTDONE1: 0x%08x\n",
DRM_DEBUG(" ACTHD: 0x%08x\n",
}
if (eir & GM45_ERROR_PAGE_TABLE) {
DRM_DEBUG("page table error\n");
DRM_DEBUG(" PGTBL_ER: 0x%08x\n",
}
}
if (eir & I915_ERROR_PAGE_TABLE) {
DRM_DEBUG("page table error\n");
DRM_DEBUG(" PGTBL_ER: 0x%08x\n",
}
}
if (eir & I915_ERROR_MEMORY_REFRESH) {
DRM_DEBUG("memory refresh error:\n");
DRM_DEBUG("pipe %c stat: 0x%08x\n",
/* pipestat has already been acked */
}
if (eir & I915_ERROR_INSTRUCTION) {
DRM_DEBUG("instruction error\n");
DRM_DEBUG(" INSTPM: 0x%08x\n",
DRM_DEBUG(" IPEIR: 0x%08x\n",
DRM_DEBUG(" IPEHR: 0x%08x\n",
DRM_DEBUG(" INSTDONE: 0x%08x\n",
DRM_DEBUG(" ACTHD: 0x%08x\n",
} else {
DRM_DEBUG(" IPEIR: 0x%08x\n",
DRM_DEBUG(" IPEHR: 0x%08x\n",
DRM_DEBUG(" INSTDONE: 0x%08x\n",
DRM_DEBUG(" INSTPS: 0x%08x\n",
DRM_DEBUG(" INSTDONE1: 0x%08x\n",
DRM_DEBUG(" ACTHD: 0x%08x\n",
}
}
if (eir) {
/*
* some errors might have become stuck,
* mask them.
*/
}
}
/**
* i915_handle_error - handle an error interrupt
* @dev: drm device
*
* Do some basic checking of regsiter state at error interrupt time and
* dump it to the syslog. Also call i915_capture_error_state() to make
* sure we get a record and make it available in debugfs. Fire a uevent
* so userspace knows something bad happened (should trigger collection
* of a ring dump etc.).
*/
{
int i;
if (wedged) {
/*
* Wakeup waiting processes so they don't hang
*/
}
}
{
unsigned long flags;
bool stall_detected;
/* Ignore early vblank irqs */
if (intel_crtc == NULL)
return;
!work->enable_stall_check) {
/* Either the pending flip IRQ arrived, or we're too early. Don't check */
return;
}
/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
} else {
}
if (stall_detected) {
DRM_DEBUG_DRIVER("Pageflip stall detected\n");
}
}
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
{
unsigned long irqflags;
return -EINVAL;
else
/* maintain vblank delivery even in deep C-states */
return 0;
}
{
unsigned long irqflags;
return -EINVAL;
return 0;
}
{
unsigned long irqflags;
return -EINVAL;
return 0;
}
{
unsigned long irqflags;
return -EINVAL;
if (pipe == 0)
else
return 0;
}
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
{
unsigned long irqflags;
}
{
unsigned long irqflags;
}
{
unsigned long irqflags;
}
{
unsigned long irqflags;
if (pipe == 0)
else
}
static u32
{
struct drm_i915_gem_request, list);
}
static bool
{
}
static struct intel_ring_buffer *
{
return NULL;
/* ACTHD is likely pointing to the dword after the actual command,
* so scan backwards until we find the MBOX.
*/
do {
break;
acthd -= 4;
return NULL;
} while (1);
}
{
return -1;
/* cursory check for an unkickable deadlock */
return -1;
}
{
int i;
}
static enum intel_ring_hangcheck_action
{
return active;
return hung;
/* Is the chip hanging on a WAIT_FOR_EVENT?
* If so we can simply poke the RB_WAIT bit
* and break the hang. This should work on
* all but the second generation chipsets.
*/
DRM_ERROR("Kicking stuck wait on %s\n",
return kick;
}
switch (semaphore_passed(ring)) {
default:
return hung;
case 1:
DRM_ERROR("Kicking stuck semaphore on %s\n",
return kick;
case 0:
return wait;
}
}
return hung;
}
/**
* This is called when the chip hasn't reported back with completed
* batchbuffers in a long time. The first time this is called we simply record
* ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
* Further, acthd is inspected to see if the ring is stuck. On stuck case
* we kick the ring. If we see no progress on three subsequent calls
* again, we assume the chip is wedged and try to fix it.
*/
{
int i;
if (!i915_enable_hangcheck)
return;
bool busy = true;
/* Issue a wake-up to catch stuck h/w. */
DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
} else
busy = false;
} else {
int score = 0;
/* We always increment the hangcheck score
* if the ring is busy and still processing
* the same request, so that no single request
* can run indefinitely (such as a chain of
* batches). The only time we do not increment
* the hangcheck score on this ring, if this
* ring is in a legitimate wait for another
* ring. In that case the waiting ring is a
* victim and we want to be sure we catch the
* right culprit. Then every time we do kick
* the ring, add a small increment to the
* score so that we can catch a batch that is
* being repeatedly kicked and so responsible
* for stalling the machine.
*/
acthd);
case wait:
score = 0;
break;
case active:
break;
case kick:
break;
case hung:
stuck[i] = true;
break;
}
}
} else {
/* Gradually reduce the count so that we catch DoS
* attempts across multiple batches.
*/
}
busy_count += busy;
}
DRM_ERROR("%s on %s\n",
rings_hung++;
}
}
if (rings_hung) {
i915_handle_error(dev, true);
return;
}
if (busy_count)
/* Reset timer case chip hangs without another request
* being added */
}
{
if (HAS_PCH_NOP(dev))
return;
/* south display irq */
/*
* SDEIER is also touched by the interrupt handler to work around missed
* PCH interrupts. Hence we can't update it after the interrupt handler
* is enabled - instead we unconditionally enable all PCH interrupt
* sources here, but then only unmask them as needed with SDEIMR.
*/
}
/* drm_dma.h hooks
*/
{
/* XXX hotplug from PCH */
/* and GT */
}
{
/* XXX hotplug from PCH */
/* and GT */
/* Power management */
}
{
int pipe;
/* VLV magic */
I915_WRITE(VLV_IMR, 0);
/* and GT */
}
{
if (HAS_PCH_IBX(dev)) {
mask &= ~SDE_HOTPLUG_MASK;
} else {
mask &= ~SDE_HOTPLUG_MASK_CPT;
}
/*
* Enable digital hotplug on the PCH, and configure the DP short pulse
* duration to 2ms (which is the minimum in the Display Port spec)
*
* This register is the same on all known PCH chips.
*/
}
{
if (HAS_PCH_NOP(dev))
return;
if (HAS_PCH_IBX(dev)) {
} else {
}
}
{
unsigned long irqflags;
/* enable kind of interrupts always enabled */
/* should always can generate irq */
/* LINTED */
dev_priv->gt_irq_mask = ~0;
else
if (IS_IRONLAKE_M(dev)) {
/* Enable PCU event interrupts
*
* spinlocking not required here for correctness since interrupt
* setup is guaranteed to run in single-threaded context. But we
* need it to make the assert_spin_locked happy. */
}
return 0;
}
{
/* enable kind of interrupts always enabled */
/* should always can generate irq */
/* LINTED */
* make sure to set a known state for only the non-RPS bits.
* The RMW is extra paranoia since this should be called after being set
* to a known state in preinstall.
* */
return 0;
}
{
/*
* toggle them based on usage.
*/
/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
#endif
return 0;
}
{
int pipe;
if (!dev_priv)
return;
}
{
if (!dev_priv)
return;
if (HAS_PCH_NOP(dev))
return;
}
{
int pipe;
}
{
/* Unmask the interrupts that we always want on. */
/* LINTED */
return 0;
}
/*
* Returns true when a page flip has completed.
*/
{
return false;
if ((iir & flip_pending) == 0)
return false;
/* We detect FlipDone by looking for the change in PendingFlip from '1'
* to '0' on the following vblank, i.e. IIR has the Pendingflip
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
* the flip is completed (no longer pending). Since this doesn't raise
* an interrupt per se, we watch for the change at vblank.
*/
return false;
return true;
}
{
/* LINTED */
unsigned long irqflags;
int pipe;
if (iir == 0)
return IRQ_NONE;
/* Can't rely on pipestat interrupt bit in iir as it might
* have been cleared after the pipestat interrupt was received.
* It doesn't set the bit in iir again, but it still produces
* interrupts (for non-MSI).
*/
i915_handle_error(dev, false);
/*
* Clear the PIPE*STAT regs before the IIR
*/
DRM_DEBUG_DRIVER("pipe %c underrun\n",
}
}
if (iir & I915_USER_INTERRUPT)
if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
}
return IRQ_HANDLED;
}
{
int pipe;
/* Clear enable bits; then clear status bits */
}
}
{
int pipe;
if (I915_HAS_HOTPLUG(dev)) {
}
}
{
/* Unmask the interrupts that we always want on. */
/* LINTED */
if (I915_HAS_HOTPLUG(dev)) {
/* Enable in IER... */
/* and unmask in IMR */
}
return 0;
}
/*
* Returns true when a page flip has completed.
*/
{
return false;
if ((iir & flip_pending) == 0)
return false;
/* We detect FlipDone by looking for the change in PendingFlip from '1'
* to '0' on the following vblank, i.e. IIR has the Pendingflip
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
* the flip is completed (no longer pending). Since this doesn't raise
* an interrupt per se, we watch for the change at vblank.
*/
return false;
return true;
}
{
/* LINTED */
unsigned long irqflags;
do {
/* Can't rely on pipestat interrupt bit in iir as it might
* have been cleared after the pipestat interrupt was received.
* It doesn't set the bit in iir again, but it still produces
* interrupts (for non-MSI).
*/
i915_handle_error(dev, false);
/* Clear the PIPE*STAT regs before the IIR */
DRM_DEBUG_DRIVER("pipe %c underrun\n",
irq_received = true;
}
}
if (!irq_received)
break;
/* Consume port. Then clear IIR or we'll miss events */
if ((I915_HAS_HOTPLUG(dev)) &&
(iir & I915_DISPLAY_PORT_INTERRUPT)) {
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
}
if (iir & I915_USER_INTERRUPT)
}
/* With MSI, interrupts are only generated when iir
* transitions from zero to nonzero. If another bit got
* set while we were handling the existing iir bits, then
* we would never get another interrupt.
*
* This is fine on non-MSI as well, as if we hit this path
* we avoid exiting the interrupt handler only to generate
* another one.
*
* Note that for MSI this could cause a stray interrupt report
* if an interrupt landed in the time between writing IIR and
* the posting read. This should be rare enough to never
* trigger the 99% of 100,000 interrupts test for disabling
* stray interrupts.
*/
ret = IRQ_HANDLED;
return ret;
}
{
int pipe;
if (I915_HAS_HOTPLUG(dev)) {
}
/* Clear enable bits; then clear status bits */
}
}
{
int pipe;
}
{
/* Unmask the interrupts that we always want on. */
/* LINTED */
/*
* Enable some error detection, note the instruction error mask
* bit is reserved, so we leave it masked.
*/
/* LINTED */
} else {
/* LINTED */
}
return 0;
}
{
if (I915_HAS_HOTPLUG(dev)) {
/* Note HDMI and DP share hotplug bits */
/* enable bits are the same for all generations */
/* Programming the CRT detection parameters tends
to generate a spurious hotplug event about three
seconds later. So just do it once.
*/
/* Ignore TV since it's buggy */
}
}
{
/* LINTED */
unsigned long irqflags;
int irq_received;
for (;;) {
/* Can't rely on pipestat interrupt bit in iir as it might
* have been cleared after the pipestat interrupt was received.
* It doesn't set the bit in iir again, but it still produces
* interrupts (for non-MSI).
*/
i915_handle_error(dev, false);
/*
* Clear the PIPE*STAT regs before the IIR
*/
DRM_DEBUG_DRIVER("pipe %c underrun\n",
irq_received = 1;
}
}
if (!irq_received)
break;
ret = IRQ_HANDLED;
/* Consume port. Then clear IIR or we'll miss events */
if (iir & I915_DISPLAY_PORT_INTERRUPT) {
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
}
if (iir & I915_USER_INTERRUPT)
if (iir & I915_BSD_USER_INTERRUPT)
}
/* With MSI, interrupts are only generated when iir
* transitions from zero to nonzero. If another bit got
* set while we were handling the existing iir bits, then
* we would never get another interrupt.
*
* This is fine on non-MSI as well, as if we hit this path
* we avoid exiting the interrupt handler only to generate
* another one.
*
* Note that for MSI this could cause a stray interrupt report
* if an interrupt landed in the time between writing IIR and
* the posting read. This should be rare enough to never
* trigger the 99% of 100,000 interrupts test for disabling
* stray interrupts.
*/
}
return ret;
}
{
int pipe;
if (!dev_priv)
return;
}
{
unsigned long irqflags;
int i;
continue;
DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
}
}
}
}
{
(void *) dev);
(void *) dev_priv);
}
else
if (IS_VALLEYVIEW(dev)) {
} else if (HAS_PCH_SPLIT(dev)) {
} else {
} else {
}
}
}
{
unsigned long irqflags;
int i;
for (i = 1; i < HPD_NUM_PINS; i++) {
}
}
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked checks happy. */
}