Searched refs:pCpu (Results 1 - 25 of 30) sorted by relevance

12

/vbox/src/VBox/VMM/VMMRC/
H A DIOMRC.cpp66 * @param pCpu Disassembler CPU state.
68 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
70 switch (pCpu->pCurInstr->uOpcode)
73 return IOMInterpretIN(pVM, pVCpu, pRegFrame, pCpu);
76 return IOMInterpretOUT(pVM, pVCpu, pRegFrame, pCpu);
80 return IOMInterpretINS(pVM, pVCpu, pRegFrame, pCpu);
84 return IOMInterpretOUTS(pVM, pVCpu, pRegFrame, pCpu);
90 AssertMsgFailed(("Unknown I/O port access opcode %d.\n", pCpu->pCurInstr->uOpcode));
H A DTRPMRCHandlers.cpp789 * @param pCpu The opcode info.
792 static int trpmGCTrap0dHandlerRing0(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC) argument
800 switch (pCpu->pCurInstr->uOpcode)
806 pCpu->Param1.fUse = DISUSE_IMMEDIATE8;
807 pCpu->Param1.uValue = 3;
811 Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
813 if (pCpu->Param1.uValue == 3)
822 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
837 rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu);
900 trpmGCTrap0dHandlerRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR PC) argument
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/vbox/src/VBox/HostDrivers/Support/testcase/
H A DtstGIP-2.cpp160 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu]; local
163 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
170 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
188 pCpu->u64NanoTS,
189 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
190 pCpu->u64TSC,
191 pCpu->u32UpdateIntervalTSC,
192 pCpu->iTSCHistoryHead,
193 pCpu->u32TransactionId,
194 pCpu
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/vbox/src/VBox/VMM/include/
H A DCSAMInternal.h235 * @param pCpu CPU disassembly state
241 typedef int (VBOXCALL *PFN_CSAMR3ANALYSE)(PVM pVM, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pInstrGC, RCPTRTYPE(uint8_t *) pCurInstrGC, PCSAMP2GLOOKUPREC pCacheRec, void *pUserData);
247 * @param pCpu Disassembly state of instruction.
250 inline RTRCPTR CSAMResolveBranch(PDISCPUSTATE pCpu, RTRCPTR pBranchInstrGC) argument
253 if (pCpu->Param1.fUse & DISUSE_IMMEDIATE8_REL)
255 disp = (int32_t)(char)pCpu->Param1.uValue;
258 if (pCpu->Param1.fUse & DISUSE_IMMEDIATE16_REL)
260 disp = (int32_t)(uint16_t)pCpu->Param1.uValue;
263 if (pCpu->Param1.fUse & DISUSE_IMMEDIATE32_REL)
265 disp = (int32_t)pCpu
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H A DPATMInternal.h619 * @param pCpu CPU disassembly state
625 typedef int (VBOXCALL *PFN_PATMR3ANALYSE)(PVM pVM, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pInstrGC, RCPTRTYPE(uint8_t *) pCurInstrGC, PPATMP2GLOOKUPREC pCacheRec);
627 int patmR3InstallGuestSpecificPatch(PVM pVM, PDISCPUSTATE pCpu, RTRCPTR pInstrGC, uint8_t *pInstrHC, PPATMPATCHREC pPatchRec);
632 int patmR3PatchInstrInt3(PVM pVM, RTRCPTR pInstrGC, R3PTRTYPE(uint8_t *) pInstrHC, DISCPUSTATE *pCpu, PPATCHINFO pPatch);
657 * @param pCpu Disassembly state of instruction.
660 DECLINLINE(RTRCPTR) PATMResolveBranch(PDISCPUSTATE pCpu, RTRCPTR pBranchInstrGC) argument
663 if (pCpu->Param1.fUse & DISUSE_IMMEDIATE8_REL)
665 disp = (int32_t)(char)pCpu->Param1.uValue;
668 if (pCpu->Param1.fUse & DISUSE_IMMEDIATE16_REL)
670 disp = (int32_t)(uint16_t)pCpu
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H A DIOMInternal.h461 bool iomGetRegImmData(PDISCPUSTATE pCpu, PCDISOPPARAM pParam, PCPUMCTXCORE pRegFrame, uint64_t *pu64Data, unsigned *pcbSize);
462 bool iomSaveDataToReg(PDISCPUSTATE pCpu, PCDISOPPARAM pParam, PCPUMCTXCORE pRegFrame, uint64_t u64Data);
/vbox/include/VBox/vmm/
H A Dcpumdis.h40 VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix);
H A Diom.h273 VMMDECL(VBOXSTRICTRC) IOMInterpretOUT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
274 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
277 VMMDECL(VBOXSTRICTRC) IOMInterpretINS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
279 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
294 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);
/vbox/src/VBox/VMM/VMMR3/
H A DPATMPatch.h24 int patmPatchGenSxDT(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC);
25 int patmPatchGenSldtStr(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC);
26 int patmPatchGenMovControl(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu);
27 int patmPatchGenMovDebug(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu);
28 int patmPatchGenMovFromSS(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC);
37 int patmPatchGenDuplicate(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pCurInstrGC);
42 int patmPatchGenCall(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pInstrGC, RTRCPTR pTargetGC, bool fIndirect);
43 int patmPatchGenRet(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pCurInstrGC);
53 * @param pCpu Disassembly state
56 int patmPatchGenJump(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPT
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H A DPATMPatch.cpp471 int patmPatchGenDuplicate(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pCurInstrGC) argument
473 uint32_t const cbInstrShutUpGcc = pCpu->cbInstr;
716 int patmPatchGenCall(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC, RTRCPTR pTargetGC, bool fIndirect) argument
738 Assert(pCpu->Param1.cb == 4);
739 Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J);
746 if (pCpu->fPrefix & DISPREFIX_SEG)
747 pPB[offset++] = DISQuerySegPrefixByte(pCpu);
749 pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, 6 /* group 5 */, pCpu->ModRM.Bits.Rm);
751 if (pCpu
818 patmPatchGenJump(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC) argument
890 patmPatchGenRet(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pCurInstrGC) argument
1194 patmPatchGenMovDebug(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu) argument
1244 patmPatchGenMovControl(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu) argument
1308 patmPatchGenMovFromSS(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC) argument
1359 patmPatchGenSldtStr(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC) argument
1460 patmPatchGenSxDT(PVM pVM, PPATCHINFO pPatch, DISCPUSTATE *pCpu, RTRCPTR pCurInstrGC) argument
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H A DPATMGuest.cpp173 * @param pCpu Disassembly state of instruction.
179 int PATMPatchOpenBSDHandlerPrefix(PVM pVM, PDISCPUSTATE pCpu, RTGCPTR32 pInstrGC, uint8_t *pInstrHC, PPATMPATCHREC pPatchRec) argument
197 return patmR3PatchInstrInt3(pVM, pInstrGC, pInstrHC, pCpu, &pPatchRec->patch);
205 * @param pCpu Disassembly state of instruction.
212 int patmR3InstallGuestSpecificPatch(PVM pVM, PDISCPUSTATE pCpu, RTGCPTR32 pInstrGC, uint8_t *pInstrHC, PPATMPATCHREC pPatchRec) argument
217 switch (pCpu->pCurInstr->uOpcode)
237 if (pCpu->pCurInstr->fParam1 == OP_PARM_REG_CS)
238 return PATMPatchOpenBSDHandlerPrefix(pVM, pCpu, pInstrGC, pInstrHC, pPatchRec);
243 AssertMsgFailed(("PATMInstallGuestSpecificPatch: unknown opcode %d\n", pCpu->pCurInstr->uOpcode));
H A DPATM.cpp669 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput)
680 pCpu, pcbInstr, pszOutput, cbOutput));
685 PDISCPUSTATE pCpu, uint32_t *pcbInstr)
696 pCpu, pcbInstr));
702 PDISCPUSTATE pCpu, uint32_t *pcbInstr)
711 pCpu, pcbInstr));
1428 * @param pCpu CPU disassembly state
1434 static int patmAnalyseBlockCallback(PVM pVM, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pInstrGC, RCPTRTYPE(uint8_t *) pCurInstrGC, PPATMP2GLOOKUPREC pCacheRec) argument
1460 if ( (pCpu->pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
1461 && (pCpu
668 patmR3DisInstrToStr(PVM pVM, PPATCHINFO pPatch, RTGCPTR32 InstrGCPtr32, uint8_t *pbInstrHC, uint32_t fReadFlags, PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput) argument
684 patmR3DisInstr(PVM pVM, PPATCHINFO pPatch, RTGCPTR32 InstrGCPtr32, uint8_t *pbInstrHC, uint32_t fReadFlags, PDISCPUSTATE pCpu, uint32_t *pcbInstr) argument
700 patmR3DisInstrNoStrOpMode(PVM pVM, PPATCHINFO pPatch, RTGCPTR32 InstrGCPtr32, uint8_t *pbInstrHC, uint32_t fReadFlags, PDISCPUSTATE pCpu, uint32_t *pcbInstr) argument
1602 patmAnalyseFunctionCallback(PVM pVM, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pInstrGC, RCPTRTYPE(uint8_t *) pCurInstrGC, PPATMP2GLOOKUPREC pCacheRec) argument
1713 patmRecompileCallback(PVM pVM, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pInstrGC, RCPTRTYPE(uint8_t *) pCurInstrGC, PPATMP2GLOOKUPREC pCacheRec) argument
2198 patmr3DisasmCallback(PVM pVM, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pInstrGC, RCPTRTYPE(uint8_t *) pCurInstrGC, PPATMP2GLOOKUPREC pCacheRec) argument
3652 patmReplaceFunctionCall(PVM pVM, DISCPUSTATE *pCpu, RTRCPTR pInstrGC, PPATMP2GLOOKUPREC pCacheRec) argument
3756 patmPatchMMIOInstr(PVM pVM, RTRCPTR pInstrGC, DISCPUSTATE *pCpu, PPATMP2GLOOKUPREC pCacheRec) argument
3928 patmR3PatchInstrInt3(PVM pVM, RTRCPTR pInstrGC, R3PTRTYPE(uint8_t *) pInstrHC, DISCPUSTATE *pCpu, PPATCHINFO pPatch) argument
3974 patmPatchJump(PVM pVM, RTRCPTR pInstrGC, R3PTRTYPE(uint8_t *) pInstrHC, DISCPUSTATE *pCpu, PPATMPATCHREC pPatchRec) argument
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H A DCSAM.cpp810 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput)
815 pCpu, pcbInstr, pszOutput, cbOutput);
821 pCpu, pcbInstr, pszOutput, cbOutput);
823 csamR3ReadBytes, &DisInfo, pCpu, pcbInstr);
832 * @param pCpu CPU disassembly state
839 static int CSAMR3AnalyseCallback(PVM pVM, DISCPUSTATE *pCpu, RCPTRTYPE(uint8_t *) pInstrGC, RCPTRTYPE(uint8_t *) pCurInstrGC, argument
846 switch (pCpu->pCurInstr->uOpcode)
849 Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
850 if (pCpu->Param1.uValue == 3)
872 switch (pCpu
809 csamR3DISInstr(PVM pVM, RTRCPTR InstrGC, uint8_t *InstrHC, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput) argument
[all...]
/vbox/src/VBox/VMM/VMMR0/
H A DHMSVMR0.h42 VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
44 VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS HCPhysCpuPage, bool fEnabledBySystem,
46 VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
H A DHMR0.cpp88 DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
92 DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94 DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
227 static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
229 NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
238 static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, argument
241 NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
245 static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage) argument
247 NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
838 PHMGLOBALCPUINFO pCpu local
1003 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu]; local
1333 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu]; local
1374 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu]; local
1413 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu]; local
1466 PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()]; local
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H A DHMVMXR0.h31 VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
33 VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys, bool fEnabledBySystem,
35 VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
H A DGVMMR0.cpp2177 PGVMMHOSTCPU pCpu = (PGVMMHOSTCPU)pvUser; local
2183 if (pCpu->u32Magic != GVMMHOSTCPU_MAGIC)
2189 RTSpinlockAcquire(pCpu->Ppt.hSpinlock);
2191 if (++pCpu->Ppt.iTickHistorization >= pCpu->Ppt.cTicksHistoriziationInterval)
2196 uint32_t iHzHistory = ++pCpu->Ppt.iHzHistory % RT_ELEMENTS(pCpu->Ppt.aHzHistory);
2197 pCpu->Ppt.aHzHistory[iHzHistory] = pCpu->Ppt.uDesiredHz;
2198 pCpu
2277 PGVMMHOSTCPU pCpu = &pGVMM->aHostCpus[iCpu]; local
[all...]
H A DHMSVMR0.cpp322 * @param pCpu Pointer to the CPU info struct.
329 VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost, argument
354 pCpu->fIgnoreAMDVInUseError = true;
357 if (!pCpu->fIgnoreAMDVInUseError)
379 pCpu->fFlushAsidBeforeUse = true;
384 ++pCpu->cTlbFlushes;
394 * @param pCpu Pointer to the CPU info struct.
398 VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage) argument
404 NOREF(pCpu);
862 PHMGLOBALCPUINFO pCpu
[all...]
H A DHMVMXR0.cpp1061 * @param pCpu Pointer to the global CPU info struct.
1072 VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost, argument
1075 Assert(pCpu);
1095 pCpu->fFlushAsidBeforeUse = false;
1098 pCpu->fFlushAsidBeforeUse = true;
1101 ++pCpu->cTlbFlushes;
1111 * @param pCpu Pointer to the global CPU info struct.
1118 VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage) argument
1120 NOREF(pCpu);
1865 * @param pCpu Pointe
1869 hmR0VmxFlushTaggedTlbNone(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
1903 hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
2029 hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
2096 hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
2208 hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
5230 PHMGLOBALCPUINFO pCpu; local
5311 PHMGLOBALCPUINFO pCpu = NULL; local
8158 VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu) argument
8757 PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu(); local
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/vbox/src/VBox/Runtime/testcase/
H A DtstLdrDisasmTest.cpp99 inline int MyDisasm(uintptr_t CodeIndex, PDISCPUSTATE pCpu, uint32_t *pcb) argument
102 int rc = DISInstrWithReader(CodeIndex, DISCPUMODE_32BIT, DisasmTest1ReadCode, 0, pCpu, &cb);
105 rc, cb, pCpu->bOpCode, pCpu->pCurInstr, 42)); \
/vbox/src/VBox/VMM/VMMAll/
H A DIOMAllMMIO.cpp579 * @param pCpu Disassembler CPU state.
583 static int iomInterpretMOVxXRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, argument
592 unsigned cb = DISGetParamSize(pCpu, &pCpu->Param2);
603 if (pCpu->pCurInstr->uOpcode == OP_MOVSX)
622 bool fRc = iomSaveDataToReg(pCpu, &pCpu->Param1, pRegFrame, u64Data);
640 * @param pCpu Disassembler CPU state.
644 static int iomInterpretMOVxXWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, argument
655 bool fRc = iomGetRegImmData(pCpu,
720 iomInterpretMOVS(PVM pVM, bool fWriteAccess, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, PSTAMPROFILE *ppStat) argument
980 iomInterpretSTOS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1114 iomInterpretLODS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1167 iomInterpretCMP(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1228 iomInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, PFNEMULATEPARAM3 pfnEmulate) argument
1328 iomInterpretTEST(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1388 iomInterpretBT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
1433 iomInterpretXCHG(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) argument
2225 IOMInterpretINS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
2394 IOMInterpretOUTS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
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H A DIOMAll.cpp66 * @param pCpu Pointer to current disassembler context.
72 bool iomGetRegImmData(PDISCPUSTATE pCpu, PCDISOPPARAM pParam, PCPUMCTXCORE pRegFrame, uint64_t *pu64Data, unsigned *pcbSize) argument
74 NOREF(pCpu);
161 * @param pCpu Pointer to current disassembler context.
166 bool iomSaveDataToReg(PDISCPUSTATE pCpu, PCDISOPPARAM pParam, PCPUMCTXCORE pRegFrame, uint64_t u64Data) argument
168 NOREF(pCpu);
910 * @param pCpu Disassembler CPU state.
912 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
924 bool fRc = iomGetRegImmData(pCpu, &pCpu
973 IOMInterpretOUT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
[all...]
H A DPATMAll.cpp481 * @param pCpu Disassembly state.
483 VMMDECL(int) PATMSysCall(PVM pVM, PCPUMCTX pCtx, PDISCPUSTATE pCpu) argument
488 if (pCpu->pCurInstr->uOpcode == OP_SYSENTER)
515 if (pCpu->pCurInstr->uOpcode == OP_SYSEXIT)
534 if (pCpu->pCurInstr->uOpcode == OP_SYSCALL)
539 if (pCpu->pCurInstr->uOpcode == OP_SYSRET)
/vbox/src/VBox/Runtime/r0drv/solaris/
H A Dtimer-r0drv-solaris.c319 * @param pCpu Pointer to the CPU on which it will fire.
321 * specified in @a pCpu.
327 static void rtTimerSolOmniCpuOnline(void *pvArg, cpu_t *pCpu, cyc_handler_t *pCyclicHandler, cyc_time_t *pCyclicTime) argument
331 AssertPtrReturnVoid(pCpu);
334 uint32_t const iCpu = pCpu->cpu_id; /* Note! CPU is not necessarily the same as pCpu. */
/vbox/src/VBox/HostDrivers/Support/
H A DSUPDrvGip.cpp127 static void supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS, uint64_t uCpuHz);
1657 * @param pCpu Pointer to which GIP CPU to initalize.
1661 static void supdrvGipInitCpu(PSUPGLOBALINFOPAGE pGip, PSUPGIPCPU pCpu, uint64_t u64NanoTS, uint64_t uCpuHz)
1663 pCpu->u32TransactionId = 2;
1664 pCpu->u64NanoTS = u64NanoTS;
1665 pCpu->u64TSC = ASMReadTSC();
1666 pCpu->u64TSCSample = GIP_TSC_DELTA_RSVD;
1667 pCpu->i64TSCDelta = pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_ZERO_CLAIMED ? INT64_MAX : 0;
1669 ASMAtomicWriteSize(&pCpu->enmState, SUPGIPCPUSTATE_INVALID);
1670 ASMAtomicWriteSize(&pCpu
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