Cross Reference: /vbox/src/VBox/VMM/VMMR0/HMR0.cpp

Lines Matching refs:pCpu
88     DECLR0CALLBACKMEMBER(int,  pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
92     DECLR0CALLBACKMEMBER(int,  pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94     DECLR0CALLBACKMEMBER(int,  pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
227 static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
229     NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
238 static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
241     NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
245 static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
247     NOREF(pCpu);  NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
838     PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
842     Assert(!pCpu->fConfigured);
845     pCpu->idCpu = idCpu;
850         rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
853         AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
854         void    *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
855         RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
858             rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
860             rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
864         pCpu->fConfigured = true;
1003     PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1009     Assert(!pCpu->fConfigured || pCpu->hMemObj != NIL_RTR0MEMOBJ);
1012     if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1013         return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1016     if (pCpu->fConfigured)
1018         void    *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
1019         RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1021         rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1024         pCpu->fConfigured = false;
1025         pCpu->idCpu = NIL_RTCPUID;
1333     PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1334     AssertPtr(pCpu);
1337     if (!pCpu->fConfigured)
1343     Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1374     PHMGLOBALCPUINFO pCpu  = &g_HvmR0.aCpuInfo[idCpu];
1375     Assert(pCpu);
1378     rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1413     PHMGLOBALCPUINFO pCpu  = &g_HvmR0.aCpuInfo[idCpu];
1416         && pCpu->fConfigured)
1420         Assert(!pCpu->fConfigured);
1421         Assert(pCpu->idCpu == NIL_RTCPUID);
1466         PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1468         Assert(pCpu->fConfigured);
1691     PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1692     AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1695     void    *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
1696     RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1697     return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1723         PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1724         AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1726         void           *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
1727         RTHCPHYS        HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1728         VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);