Cross Reference: /vbox/src/VBox/VMM/VMMR0/HMSVMR0.cpp

Lines Matching refs:pCpu
322  * @param   pCpu            Pointer to the CPU info struct.
329 VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
354             pCpu->fIgnoreAMDVInUseError = true;
357         if (!pCpu->fIgnoreAMDVInUseError)
379     pCpu->fFlushAsidBeforeUse = true;
384     ++pCpu->cTlbFlushes;
394  * @param   pCpu            Pointer to the CPU info struct.
398 VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
404     NOREF(pCpu);
862     PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
871     Assert(pCpu->idCpu != NIL_RTCPUID);
872     if (   pVCpu->hm.s.idLastCpu   != pCpu->idCpu
873         || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
897         pCpu->uCurrentAsid               = 1;
899         pVCpu->hm.s.cTlbFlushes          = pCpu->cTlbFlushes;
912             ++pCpu->uCurrentAsid;
914             if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
916                 pCpu->uCurrentAsid        = 1;      /* Wraparound at 1; host uses 0 */
917                 pCpu->cTlbFlushes++;                /* All VCPUs that run on this host CPU must use a new VPID. */
923                     pCpu->fFlushAsidBeforeUse = true;
928                     pCpu->fFlushAsidBeforeUse = false;
933                 && pCpu->fFlushAsidBeforeUse)
940                     pCpu->fFlushAsidBeforeUse = false;
944             pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
945             pVCpu->hm.s.idLastCpu    = pCpu->idCpu;
946             pVCpu->hm.s.cTlbFlushes  = pCpu->cTlbFlushes;
985     AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
986               ("vcpu idLastCpu=%x pcpu idCpu=%x\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
987     AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
988               ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
989     AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
990               ("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
992               ("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1711  * @param   pCpu        Pointer to the CPU info struct.
1713 VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1719     NOREF(pVM); NOREF(pCpu);
3751  * @param   pCpu            Pointer to the disassembler state.
3754 static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
3759     int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);