Searched refs:X86_DR7_RA1_MASK (Results 1 - 10 of 10) sorted by relevance

/vbox/src/VBox/VMM/VMMAll/
H A DDBGFAll.cpp38 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
H A DCPUMAllRegs.cpp1950 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
2126 pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
H A DIEMAllCImpl.cpp.h5188 drX |=X86_DR7_RA1_MASK;
5277 uNewDrX |= X86_DR7_RA1_MASK;
H A DEMAll.cpp1824 uNewDrX |= X86_DR7_RA1_MASK;
H A DIEMAll.cpp10331 if (!fRem || (pOrgCtx->dr[7] & ~X86_DR7_RA1_MASK) != (pDebugCtx->dr[7] & ~X86_DR7_RA1_MASK)) /* REM 'mov drX,greg' bug.*/
/vbox/include/iprt/
H A Dx86.h920 #define X86_DR7_RA1_MASK (RT_BIT(10)) macro
/vbox/src/VBox/VMM/VMMR0/
H A DHMSVMR0.cpp1438 Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
H A DHMVMXR0.cpp4148 Assert((pMixedCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); /* Bit 10 is reserved (RA1). */
11840 pMixedCtx->dr[7] |= X86_DR7_RA1_MASK;
/vbox/src/VBox/VMM/VMMR3/
H A DCPUM.cpp1178 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
/vbox/src/recompiler/target-i386/
H A Dop_helper.c3696 t0 |= X86_DR7_RA1_MASK;

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