Searched refs:flush (Results 1 - 8 of 8) sorted by relevance

/solaris-x11-s11/open-src/lib/DPS/sun-src/libdps/
H A Dpsioops.psw79 flush
H A Ddpsioops.psw79 flush
/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_ringbuffer.c147 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
173 * The cache flushes require the workaround flush that triggered this
229 /* Just flush everything. Experiments have shown that reducing the
327 /* Just flush everything. Experiments have shown that reducing the
1540 /* We need to add any requests required to flush the objects and ring */
1667 u32 invalidate, u32 flush)
1679 * "If ENABLED, all TLBs will be invalidated once the flush
1739 u32 invalidate, u32 flush)
1752 * "If ENABLED, all TLBs will be invalidated once the flush
1765 if (IS_GEN7(dev) && flush)
1666 gen6_bsd_ring_flush(struct intel_ring_buffer *ring, u32 invalidate, u32 flush) argument
1738 gen6_ring_flush(struct intel_ring_buffer *ring, u32 invalidate, u32 flush) argument
[all...]
H A Dintel_ringbuffer.h128 int (*flush)(struct intel_ring_buffer *ring, member in struct:intel_ring_buffer
186 * Do an explicit TLB flush before MI_SET_CONTEXT
H A Di915_gem_context.c381 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
H A Di915_drv.h1609 extern void i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);
/solaris-x11-s11/open-src/kernel/efb/src/
H A Dradeon_drm.h592 int flush; member in struct:drm_radeon_cp_stop
H A Dradeon_cp.c1036 * Reset the Command Processor. This will not flush any pending
1052 * Stop the Command Processor. This will not flush any pending
1053 * commands, so you must flush the command stream and wait for the CP
1901 if (stop.flush) {

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