Searched refs:DPLL (Results 1 - 3 of 3) sorted by relevance

/solaris-x11-s11/open-src/kernel/i915/src/
H A Dintel_dvo.c290 int dpll_reg = DPLL(pipe);
H A Dintel_display.c898 reg = DPLL(pipe);
1331 reg = DPLL(pipe);
1368 reg = DPLL(pipe);
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1386 'B' + port, I915_READ(DPLL(0)));
1476 /* Make sure PCH DPLL is enabled */
3446 /* disable PCH DPLL */
4506 I915_WRITE(DPLL(pipe), dpll);
4507 POSTING_READ(DPLL(pipe));
4510 if (wait_for(((I915_READ(DPLL(pip
[all...]
H A Di915_reg.h1214 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) macro
1263 * Selects the phase for the 10X DPLL clock for the PCIe
1290 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1296 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2089 * the DPLL semantics change when the LVDS is assigned to that pipe.
2127 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2

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