Lines Matching refs:DPLL
898 reg = DPLL(pipe);
1331 reg = DPLL(pipe);
1368 reg = DPLL(pipe);
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1386 'B' + port, I915_READ(DPLL(0)));
1476 /* Make sure PCH DPLL is enabled */
3446 /* disable PCH DPLL */
4506 I915_WRITE(DPLL(pipe), dpll);
4507 POSTING_READ(DPLL(pipe));
4510 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4511 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4593 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4594 POSTING_READ(DPLL(pipe));
4604 I915_WRITE(DPLL(pipe), dpll);
4607 POSTING_READ(DPLL(pipe));
4616 * DPLL is enabled and the clocks are stable.
4620 I915_WRITE(DPLL(pipe), dpll);
4657 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4658 POSTING_READ(DPLL(pipe));
4665 I915_WRITE(DPLL(pipe), dpll);
4668 POSTING_READ(DPLL(pipe));
4672 * DPLL is enabled and the clocks are stable.
4676 I915_WRITE(DPLL(pipe), dpll);
5011 tmp = I915_READ(DPLL(crtc->pipe));
5064 /* Ironlake: try to setup display ref clock before DPLL
5800 * DPLL is enabled and the clocks are stable.
6947 u32 dpll = I915_READ(DPLL(pipe));
6983 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7068 int dpll_reg = DPLL(pipe);
7111 int dpll_reg = DPLL(pipe);
8472 /* Set up the DPLL and any encoders state that needs to adjust or depend
8473 * on the DPLL.
8906 "PCH DPLL A",
8907 "PCH DPLL B",