/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
H A D | lm_hw_init_reset.c | 53 REG_WR(pdev,(PORT_ID(pdev) ? PXP2_REG_PSWRQ_##blk##1_L2P: PXP2_REG_PSWRQ_##blk##0_L2P),((last)<<10 | (first))); \ 55 REG_WR(pdev,PXP2_REG_RQ_##blk##_FIRST_ILT,(first)); \ 56 REG_WR(pdev,PXP2_REG_RQ_##blk##_LAST_ILT,(last)); \ 286 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 367 REG_WR(PFDEV(pdev),XSDM_REG_OPERATION_GEN, final_cleanup.command); 555 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 632 REG_WR(pdev,(GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET),MISC_REGISTERS_RESET_REG_1_RST_RBCP); 715 REG_WR( pdev, reg_arr_ptr[idx], 0 ); 746 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_CLEAR, reg_1_clear ); 756 REG_WR(pde [all...] |
H A D | lm_er.c | 94 REG_WR(pdev, MISC_REG_AEU_GENERAL_MASK, val); 106 REG_WR(pdev, PXP_REG_HST_DISCARD_DOORBELLS, enable_bit); 109 REG_WR(pdev, PXP_REG_HST_DISCARD_INTERNAL_WRITES, enable_bit); 116 REG_WR(pdev, IGU_REG_BLOCK_CONFIGURATION, val); 129 REG_WR(pdev, PXP2_REG_RD_START_INIT, 0); 130 REG_WR(pdev, PXP2_REG_RQ_RBC_DONE, 0); 189 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 192 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 195 REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2); 197 REG_WR(pde [all...] |
H A D | lm_hw_attn.c | 144 REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0); 147 REG_WR(pdev,PXP_REG_PXP_INT_MASK_1, (PXP_PXP_INT_MASK_1_REG_HST_INCORRECT_ACCESS 151 REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0); 157 REG_WR(pdev,BRB1_REG_BRB1_INT_MASK ,0xFC00); 159 REG_WR(pdev,QM_REG_QM_INT_MASK ,0); 160 REG_WR(pdev,TM_REG_TM_INT_MASK ,0); 161 REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_0 ,0); 162 REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_1 ,0); 163 REG_WR(pdev,XCM_REG_XCM_INT_MASK ,0); 164 //REG_WR(pde [all...] |
H A D | lm_nvram.c | 69 REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port_num )); 117 REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port_num)); 155 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 158 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WREN); 198 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 201 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WRDI); 240 REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN); 262 REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val & ~(MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN)); 294 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 297 REG_WR(pde [all...] |
H A D | lm_hw_access.c | 394 REG_WR(pdev,MISC_REG_SPIO_INT, val ) ; 399 REG_WR(pdev,MISC_REG_SPIO_EVENT_EN, val ) ; 584 REG_WR(pdev, MISC_REG_GPIO, gpio_reg); 648 REG_WR(pdev, MISC_REG_GPIO, gpio_reg); 715 REG_WR(pdev, MISC_REG_GPIO_INT, gpio_reg); 776 REG_WR(pdev, MISC_REG_SPIO, reg_val); 842 REG_WR(pdev, MISC_REG_SPIO, reg_val); 869 REG_WR(pdev, NIG_REG_LED_MODE_P0, mode_idx); 872 REG_WR(pdev, NIG_REG_LED_MODE_P1, mode_idx); 941 REG_WR(pde [all...] |
H A D | lm_sb.c | 102 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WOMASK(pdev)); 118 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WMASK(pdev)); 570 REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_L + 8*PORT_ID(pdev), host_sb_addr->as_u32.low); 571 REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_H + 8*PORT_ID(pdev), host_sb_addr->as_u32.high); 580 REG_WR(pdev, IGU_REG_ATTN_MSG_ADDR_L, host_sb_addr->as_u32.low); 581 REG_WR(pdev, IGU_REG_ATTN_MSG_ADDR_H, host_sb_addr->as_u32.high); 896 REG_WR(pdev, HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_INT_ACK, result); 929 REG_WR(pdev, BAR_IGU_INTMEM + cmd_addr*8, cmd_data.sb_id_and_flags); 946 REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags); 947 REG_WR(pde [all...] |
H A D | lm_power.c | 129 REG_WR( pdev, reg_len, val ) ; 132 REG_WR( pdev, reg_crc, val ) ; 255 REG_WR( pdev, offset, nwuf_reg_value ) ; 277 REG_WR( pdev, offset, nwuf_reg_value ) ; 321 REG_WR(pdev, emac_base+ offset , b_enable_mpkt ? val:0); 326 REG_WR(pdev, emac_base+ offset, b_enable_mpkt ? val:0); 379 REG_WR(pdev, emac.emac_mode, val); 383 REG_WR(pdev, rpm.rpm_config, val); 485 REG_WR(pdev, pcicfg_device_control_offset, pf0_pcie_status_control);
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H A D | lm_phy.c | 82 REG_WR(cb, reg_addr, val); 202 REG_WR(cb, MISC_REG_AEU_GENERAL_ATTN_12 + FUNC_ID((lm_device_t *)cb)*sizeof(u32), 1); 249 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1); 258 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); 267 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,tmp); 298 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); 300 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + 323 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1); 332 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,val); 341 REG_WR(pde [all...] |
H A D | lm_mcp.c | 151 REG_WR(pdev, shmem + validity_offset, 0); 240 REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15 + 4, 0xffffffff); 246 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, 253 REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15, 0xffffffff); 284 REG_WR(pdev, GRCBASE_MCP + 0x9c, val_wr); 326 REG_WR(pdev, GRCBASE_MCP + 0x9c, val);
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H A D | lm_pf.c | 381 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0); 382 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_FUNC_MASK, 0); 383 REG_WR(pf_dev, PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0); 389 REG_WR(pf_dev, 0x24d8, 1<<29); 391 REG_WR(pf_dev, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR ,(1<<ABS_FUNC_ID(pf_dev))); 392 //REG_WR(pf_dev, PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED, PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_SRIOV_DISABLED_REQUEST);*/ 973 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0); 989 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0); 1013 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, value); 1181 REG_WR(PFDE [all...] |
H A D | bnxe_hw_debug.c | 84 REG_WR(pdev,TM_REG_EN_LINEAR0_TIMER, 0); 104 REG_WR(pdev,TM_REG_EN_LINEAR1_TIMER, 0); 134 REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER,1); 137 REG_WR(pdev, TM_REG_EN_LINEAR1_TIMER,1); 208 REG_WR(pdev,PXP2_REG_RQ_HOQ_RAM_RD_REQ,vq);
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H A D | lm_niv.c | 373 REG_WR(pdev, output_offset + bytes_written, *field_ptr);
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H A D | lm_dmae.c | 808 REG_WR( pdev, 813 REG_WR(pdev, lm_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE) ;
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H A D | lm_dcbx.c | 4254 REG_WR(pdev, (admin_mib_offset + i) , *buff); 4439 REG_WR(pdev, (offset + i) , *buff); 4487 REG_WR(pdev, (offest+ i) , *buff);//Change to write
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ |
H A D | ecore_init_ops.h | 43 REG_WR(pdev, addr + i*4, data[i]); 275 REG_WR(pdev, addr, op->write.val); 519 REG_WR(pdev, read_arb_addr[i].l, read_arb_data[i][r_order].l); 520 REG_WR(pdev, read_arb_addr[i].add, 522 REG_WR(pdev, read_arb_addr[i].ubound, 530 REG_WR(pdev, write_arb_addr[i].l, 533 REG_WR(pdev, write_arb_addr[i].add, 536 REG_WR(pdev, write_arb_addr[i].ubound, 541 REG_WR(pdev, write_arb_addr[i].l, 545 REG_WR(pde [all...] |
H A D | ecore_init.h | 97 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */ 99 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */ 101 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */ 102 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */ 103 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */ 210 REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val); 234 REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr, 259 REG_WR(pdev, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 260 REG_WR(pdev, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 261 REG_WR(pde [all...] |
H A D | ecore_common.h | 51 REG_WR(pdev, addr + (i * 4), data[i]);
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H A D | ecore_sp_verbs.c | 1118 REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : 3675 REG_WR(pdev, MC_HASH_OFFSET(pdev, i), mc_filter[i]);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/ |
H A D | lm_vf.c | 182 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0); 183 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_FUNC_MASK, 0); 184 REG_WR(pf_dev, PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0); 190 REG_WR(pf_dev, 0x24d8, 1<<29); 192 REG_WR(pf_dev, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR ,(1<<ABS_FUNC_ID(pf_dev))); 193 //REG_WR(pf_dev, PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED, PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_SRIOV_DISABLED_REQUEST);*/ 355 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + XSTORM_VF_SPQ_DATA_OFFSET(ABS_VFID(pdev)) + i*sizeof(u32_t),0); 358 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(ABS_VFID(pdev))),pdev->sq_info.sq_chain.bd_chain_phy.as_u32.low); 359 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(ABS_VFID(pdev)) + 4),pdev->sq_info.sq_chain.bd_chain_phy.as_u32.high); 360 REG_WR(PFDE [all...] |
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/ |
H A D | bnxe_clc.c | 68 #define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val) macro 70 #define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val) 350 REG_WR(cb, reg, val); 359 REG_WR(cb, reg, val); 388 REG_WR(cb, params->lfa_base + 509 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 531 REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 535 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 584 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 593 REG_WR(c [all...] |
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/ |
H A D | bnxe_fw_funcs.c | 66 REG_WR(pdev, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos); 71 REG_WR(pdev, reg_addr, reg_bit_map & (~q_bit_map)); 76 REG_WR(pdev, reg_addr, reg_bit_map | q_bit_map); 87 REG_WR(pdev, reg_addr, reg_bit_map);
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/ |
H A D | lm_vf.c | 209 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + XSTORM_VF_SPQ_DATA_OFFSET(vf_info->abs_vf_id) + i*sizeof(u32_t),0); 212 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vf_info->abs_vf_id)),0); 213 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vf_info->abs_vf_id)) + 4,0); 214 REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PROD_OFFSET(vf_info->abs_vf_id)),0); 219 REG_WR(PFDEV(pdev), reg, val); 558 REG_WR(PFDEV(pdev), reg, val); 2939 REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 2940 REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 2941 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0); 2942 REG_WR(PFDE [all...] |
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/ |
H A D | lm5710.h | 180 REG_WR((_pdev), 0x2000, kuku); \ 184 #define LM_GENERAL_ATTN_INTERRUPT_SET(_pdev,_func) REG_WR((_pdev),MISC_REG_AEU_GENERAL_ATTN_12 + 4*(_func),0x1) 4091 #define REG_WR(_pdev, _reg_offset, _val) \ macro 4097 #define VF_REG_WR(_pdev, _reg_offset, _val) REG_WR(_pdev, _reg_offset, _val) 4106 #define REG_WR(_pdev, _reg_offset, _val) \ macro 4153 #define REG_WR(_pdev, _reg_offset, _val) \ macro 4194 #define REG_WR(_pdev, _reg_offset, _val) \ macro
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/illumos-gate/usr/src/uts/common/io/bnxe/ |
H A D | bnxe.h | 1026 REG_WR((lmdev), 0x2000, (data)); \
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l4/ |
H A D | lm_l4sp.c | 993 REG_WR(pdev, max_reg, ack_frequency); 1002 REG_WR(pdev, tmr_reg, delayed_ack_ticks);
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